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7606848 Detector in parallel with a logic component  
One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are...
7444367 Floating point status information accumulation circuit  
A floating point flag combining or accumulating circuit includes an analysis circuit that receives a plurality of floating point operands, each having encoded status flag information, and a result...
7430576 Floating point square root provider with embedded status information  
A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating...
7395297 Floating point system that represents status flag information within a floating point operand  
A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status...
7069289 Floating point unit for detecting and representing inexact computations without flags or traps  
A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the...
7062633 Conditional vector arithmetic method and conditional vector arithmetic unit  
It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150 , the result of the decision is retained...
7058678 Fast forwarding ALU  
An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second...
7047272 Rounding mechanisms in processors  
An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate...
7016928 Floating point status information testing circuit  
A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point...
7010562 Arithmetic circuit  
An arithmetic circuit includes an arithmetic circuit performing an arithmetic operation of a predetermined bit width in accordance with an arithmetic instruction, a holding circuit storing status...
7003543 Sticky z bit  
The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on...
6986023 Conditional execution of coprocessor instruction based on main processor arithmetic flags  
A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the...
6970898 System and method for forcing floating point status information to selected values  
A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or...
6912560 Adder with improved overflow flag generation  
An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary...
6819971 Fast computation of overflow flag in a bit manipulation unit  
A bit manipulation unit (BMU) scales and formats data and includes fast computation of the overflow flag. For fast computation the BMU's overflow flag is computed based on the input data and the...
6742013 Apparatus and method for uniformly performing comparison operations on long word operands  
Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero...
6718459 Device and method for arithmetic processing  
A numerical arithmetic circuit 50 executes an arithmetic instruction according to an instruction read out of a program memory 10 and then stores the arithmetic result into a register group 40 ...
6701338 Cumulative status of arithmetic operations  
The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the...
6629118 Zero result prediction  
A zero result detector for detecting a zero result in the sum of a first operand A, a second operand B and a carry bit Cin operates by calculating {overscore (A)} and {overscore (A)}+1 and then...
6571265 Mechanism to detect IEEE underflow exceptions on speculative floating-point operations  
A mechanism is disclosed for detecting underflow conditions for speculative floating-point operations. A floating-point status register includes a status flag which is set when a result generated...
6502119 High speed microprocessor zero detection circuit with 32-bit and 64-bit modes  
A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the...
6487576 Zero anticipation method and apparatus  
A zero anticipation mechanism for an arithmetic unit 42 of a processing engine includes an array of cells 420, 430 interconnected to produce an ordered sequence of intermediate anticipation...
6425074 Method and apparatus for rapid execution of FCOM and FSTSW  
A microprocessor configured to rapidly execute floating point store status word (FSTSW) type instructions that are immediately preceded by floating point compare (FCOM) type instructions is...
6424955 Zero detection in digital processing  
There is disclosed a digital processor having an arithmetic unit and a zero detection circuit and a method of performing zero detection in a digital processor in which a zero detection circuit is...
6334135 Data processing system and register file  
A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic...
6317824 Method and apparatus for performing integer operations in response to a result of a floating point operation  
A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and...
6247117 Apparatus and method for using checking instructions in a floating-point execution unit  
The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the...
6243731 Apparatus and method for extending register dynamic range  
An apparatus for extending register dynamic range on a processor is disclosed. The apparatus comprises a register (102) for performing a set of processor (100) operations. The apparatus further...
6188240 Programmable function block  
A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group...
6173394 Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result  
A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status...
6173303 Multiply circuit and method that detects portions of operands whose partial products are superfluous and modifies partial product manipulation accordingly  
Multiplication circuitry performs a multiply operation to multiply a multiplicand operand and a multiplier operand to form a total product of the multiplication operation, where the multiplier...
6138135 Propagating NaNs during high precision calculations using lesser precision hardware  
A floating point arithmetic unit provides consistent propagation of NaNs le performing high precision calculations on hardware designed to perform lower precision calculations. In one embodiment,...
6105047 Method and apparatus for trading performance for precision when processing denormal numbers in a computer system  
An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by...
6018757 Zero detect for binary difference  
Zero detect of a difference of binary operands is disclosed. If the difference is zero, the bit-complement of the difference is a string of one's, and therefore incrementing the string of one's...
6009511 Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers  
A superscalar microprocessor appends a tag value to each floating point number. The tag value indicates whether the corresponding floating point number is a normal floating point number or a...
6009451 Method for generating barrel shifter result flags directly from input data  
A method and apparatus for generating a flag simultaneously with production of an operation result by an operational unit. The flag is generated based on data input to the operational unit, and the...
5995993 Serial in-circuit emulator  
To debug software programs, an economical and efficient serial in-circuit emulator (ICE) according to the invention can pause the operation of a CPU to read/write current data from/to a register of...
5978901 Floating point and multimedia unit with data type reclassification capability  
A superscalar microprocessor includes a combination floating point and multimedia unit. The floating point and multimedia unit includes one set of registers. The multimedia core and floating point...
5978825 Zero detection circuitry and methods  
A method of generating zero detect flag at the output of an adder adding a first vector and a second vector to generate a third vector. A fourth vector is generated from the third vector a carry...
5975749 Zero and one detection chain for a carry select adder  
A carry select adder includes an adder for outputting a first sum of values based on a first presumed carry-in of zero and a second sum of the values based on a second presumed carry-in of one. A...
5956263 Multiplication, division and square root extraction apparatus  
A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a...
5900013 Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries  
A device and method for comparing cancel tags, and for canceling data from a finite wrap-around data buffer. The data buffer stores tag values that are continuous, or sequential. A cancel tag is...
5862066 Methods and apparatus for fast check of floating point zero or negative zero  
Apparatus for performing floating point divide operations includes a divider and a comparator. The divider performs a floating point divide operation on a floating point numerator and a floating...
5777688 Signal processor  
A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by...
5748516 Floating point processing unit with forced arithmetic results  
Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation...
5748515 Data processing condition code flags  
A data processing system incorporating an arithmetic logic unit 20, 22, 24 having an N-bit data pathway and supporting parallel operation program instruction words in which to independent...
5732005 Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation  
A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of...
5694348 Method apparatus and system for correlation  
This invention involves computing a mean squared error between a predetermined plural number of pairs of first and second values. A data processing apparatus (71, 72, 73, 74) has data registers...
5689721 Detecting overflow conditions for negative quotients in nonrestoring two's complement division  
A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients...
5684728 Data processing system having a saturation arithmetic operation function  
A data processing system includes an instruction decoder for decoding a string of instructions including an arithmetic operation instruction, an arithmetic operation unit controlled by the...
Matches 1 - 50 out of 126 1 2 3 >