Matches 51 - 100 out of 126 < 1 2 3 >
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5644521 Comparator scheme  
Method for testing whether the result of an addition or subtraction of two or more variables will equal a specified third value without actually performing an addition or subtraction operation. The...
5640578 Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section  
An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a...
5638312 Method and apparatus for generating a zero bit status flag in a microprocessor  
A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to...
5615113 Early signaling of no-overflow for nonrestoring twos complement division  
An early no-overflow signaling system and method is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--when a...
5604689 Arithmetic logic unit with zero-result prediction  
An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition...
5600583 Circuit and method for detecting if a sum of two multidigit numbers equals a third multidigit number prior to availability of the sum  
A circuit and method for detecting if a sum of a first multibit number A of N bits and a second multibit B of N bits equals a third multibit number C of N bits prior to availability of the sum of A...
5600584 Interactive formula compiler and range estimator  
A method for tracking errors in a system of numerical formulas. It uses confidence intervals and special encodings, and is suitable for use in an interactive computer program. Maximum efficiency...
5592405 Multiple operations employing divided arithmetic logic unit and multiple flags register  
A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a...
5586069 Arithmetic logic unit with zero sum prediction  
An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition...
5581496 Zero-flag generator for adder  
Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead...
5561619 Arithmetic logic unit provided with combinational circuit and zero value detector connected in parallel  
An arithmetic logic unit (ALU) is disclosed, which is capable of shortening the zero-detection time. The ALU comprises a combinational circuit, a first and second zero detectors and a selector. The...
5532938 Numerical arithmetic processing unit  
Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data...
5522085 Arithmetic engine with dual multiplier accumulator devices  
An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first...
5519649 Micro-processor having rapid condition comparison function  
A micro-processor includes an arithmetic logic unit (ALU) for executing a computer program stored in memory. The micro-processor further includes a condition comparison memory unit, such as a...
5508950 Circuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sum  
A circuit and method for detecting if a sum of a first multibit number A of N bits and a second multibit B of N bits equals a third multibit number C of N bits prior to availability of the sum of A...
5481489 Method of and apparatus for discriminating NaN  
When processing a binary floating-point number in the IEEE form, whether or not the data is NaN can be discriminated irrespective of a precision thereof. The binary floating-point number having...
5469377 Floating point computing device for simplifying procedures accompanying addition or subtraction by detecting whether all of the bits of the digits of the mantissa are 0 or 1  
A floating point computing device having a mantissa register for storing a mantissa of a floating-point number, a detecting circuit for determining the bit states of the consecutive bits of the...
5448509 Efficient hardware handling of positive and negative overflow resulting from arithmetic operations  
A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to...
5430852 Control transfer method in system with multiple arithmetic units each with independent microprogram control by transferring start address and branch condition codes  
A microprogram control system has first and second microprogram control units and first and second arithmetic circuits corresponding to the first and second microprogram control units,...
5422805 Method and apparatus for multiplying two numbers using signed arithmetic  
A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum...
5423052 Central processing unit with switchable carry and borrow flag  
For obtaining a central processing unit to perform, with the same operation code, an operation in which a carry input is effective and an operation in which the carry input is invalid or an...
5375080 Performing arithmetic on composite operands to obtain a binary outcome for each multi-bit component  
Binary outcome operations are performed on composite operands. A composite operand is an operand that includes plural multi-bit component data items. A binary outcome operation obtains, for each...
5367477 Method and apparatus for performing parallel zero detection in a data processing system  
A zero detection method (FIG. 5) and a zero detection apparatus (FIGS. 2-4) involves determining if the sum of at least two operands and a carry-in bit will produce a zero result. The zero...
5341320 Method for rapidly processing floating-point operations which involve exceptions  
A method for processing exception conditions in a floating-point system (40) begins by determining in hardware that an exception will occur (14) for a given floating-point operation and operand(s)....
5276891 Alignment of sign, data, edit byte operand results for storage in memory  
The arithmetic processor of a digital computer system has means for performing, on its output operands while they are in transit to memory for storage, such manipulations as operand alignment,...
5270955 Method of detecting arithmetic or logical computation result  
An arithmetic or logical computation result detection circuit is described. The circuit has a set of one-bit-zero cells which receive a first operand, A, a second operand, B, and a C in , and...
5262973 Method and apparatus for optimizing complex arithmetic units for trivial operands  
When an arithmetic operation is to be performed, the operands are concurrently sent to the arithmetic unit to perform the complex arithmetic operation and into an operand check mechanism which...
5258942 Balanced two-level delay propagation all one detector compiler  
An apparatus for detecting a binary word each of the bits of which has the same binary value includes a plurality of logic groups, different ones of which receive different numbers of bits of the...
5257214 Qualification of register file write enables using self-timed floating point exception flags  
A floating point processor in which floating point register file write enables are self-timed from the exception flags from the respective floating point processing units. This self-timing is...
5201056 RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output  
A RICS microprocessor architecture is provided with a plurality of data registers and instruction registers each having a multi-bit extension for extending the width of the data and instruction...
5197022 Overflow detection calculator and method of overflow determination  
A calculation method suitable for use in statistics calculations and a calculator using the method are disclosed. The method has the steps of storing a memory content from a memory in a first...
5164914 Fast overflow and underflow limiting circuit for signed adder  
In a signed binary adder circuit, limiter control circuitry detects underflow and overflow conditions, and controls combinatorial result limiter circuits in each bit position to limit the result to...
5091874 Encoder apparatus  
A high-speed encoding apparatus retrieves the bit position of either one of the lowest order bit or the highest order bit having a first logical value. Such retrieving starts from a selected...
5038313 Floating-point processor provided with high-speed detector of overflow and underflow exceptional conditions  
A processor includes an exception detector for receiving floating-point data on which a rounding operation is to be performed. The exception detector detects whether or not an overflow or an...
5038314 Method and apparatus for correction of underflow and overflow  
An apparatus is provided for correcting underflow of binary data and for correcting overflow of binary data from computation unit for producing binary data in a fixed point range comprising:...
5029069 Data processor  
A data processor which has instructions of operation and comparison when including the signed binary number represented by complement on 2 as the object and has a flag correctly representing the...
5020016 Circuit for detecting zero result of addition/subtraction by simultaneously processing each pair of corresponding bits of a pair of given numbers in parralel  
A zero detection circuit operates to detect whether or not the result of addition/subtraction between a pair of binary numbers each composed of a plurality of bits becomes zero in all the plurality...
4999796 Sticky bit detection and shifting logic  
A circuit which concurrently performs bit shifting for floating point arithmetic and sticky bit determination. An input data operand is presented to the circuit along with a control signal which...
4961161 Arithmetic processor performing mask and trap operations for exceptions  
A floating-point arithmetic processor performs a MASK or TRAP operation in response to occurrence of an exception. This processor includes a first flag which is set when the exception occurs, a...
4947359 Apparatus and method for prediction of zero arithmetic/logic results  
The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from...
4945507 Overflow correction circuit  
An overflow correction circuit is coupled to receive an output of an arithmetic operation circuit having first and second data inputs. The first data input is connected to an internal data bus so...
4924422 Method and apparatus for modified carry-save determination of arithmetic/logic zero results  
The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from...
4914581 Method and apparatus for explicitly evaluating conditions in a data processor  
In a data processor, the conditions associated with an operand are evaluated only in response to the execution of a special instruction. The results of this evaluation is provided as a result...
4907185 Program-controlled computer with an interrupt capability for floating-point operation  
A program-controlled computer includes a first unit for executing an addition or a substraction on a first floating-point data and a second floating-point data inputted thereto, a second unit for...
4890253 Predetermination of result conditions of decimal operations  
An apparatus is provided which tests the magnitude and sign digits of packed decimal binary numbers during performance of arithmetic operations which combine the numbers for the purpose of setting...
4888722 Parallel arithmetic-logic unit for as an element of digital signal processor  
A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first...
4878189 Microcomputer having Z-flag capable of detecting coincidence at high speed  
A microcomputer comprises an arithmetic and logic unit having a pair of input connected to receive a pair of n-bit data and one output for generating a n-bit data of operation result. A NOR circuit...
4847802 Method and apparatus for identifying the precision of an operand in a multiprecision floating-point processor  
An arithmetic logic unit (ALU) and a plurality of operand registers wherein each of the operand registers includes a tag cell for storing a bit identifying the precision of the operand stored...
4821225 Arithmetic and logic unit with prior state dependent logic operations  
The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of...
4815019 Fast ALU equals zero circuit  
A fast ALU=0 circuit is used with a carry-select lookahead ALU. Preliminary ALU=0 signals are derived for each section of the ALU prior to a carry in signal being received by that section. When the...
Matches 51 - 100 out of 126 < 1 2 3 >