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7525457 Transforming design objects in a computer by converting data sets between data set types  
A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type...
7509367 Method and apparatus for performing multiply-add operations on packed data  
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored...
7430577 Computationally efficient mathematical engine  
A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of...
7395294 Arithmetic logic unit  
An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality...
7353244 Dual-multiply-accumulator operation optimized for even and odd multisample calculations  
According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.
7346761 Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle  
An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing...
7212959 Method and apparatus for accumulating floating point values  
A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained....
7027598 Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7027597 Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7013321 Methods and apparatus for performing parallel integer multiply accumulate operations  
According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand...
6922716 Method and apparatus for vector processing  
A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and...
6912557 Math coprocessor  
A math coprocessor 1300 includes a multiply-accumulate unit 1600 . Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the...
6889240 Data processing device having a central processing unit and digital signal processing unit  
In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to...
6854003 Video frame rendering engine  
A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal...
6725360 Selectively processing different size data in multiplier and ALU paths in parallel  
An integrated circuit which has two separate paths for two different data widths. The first processing path processes data up to n bits in a n multiplier. A second path operates in parallel with...
6601078 Time-efficient real-time correlator  
A time-efficient real-time correlator is provided for use in a receiver of a wireless communications system. The correlator correlates a signal received by the receiver with a pseudo-random number...
6574651 Method and apparatus for arithmetic operation on vectored data  
A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in...
6571268 Multiplier accumulator circuits  
A multiply-accumulate (MAC) unit, having a first binary operand X, a second binary operand Y, a third binary operand, Booth recode logic for generating a plurality of partial products from said...
6526430 Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)  
The proposed architecture is integrated onto a Digital Signal Processor (DSP) as a coprocessor to assist in the computation of sum of absolute differences, symmetrical row/column Finite Impulse...
6493817 Floating-point unit which utilizes standard MAC units for performing SIMD operations  
The present invention provides a method and apparatus for performing floating-point operations. The apparatus of the present invention comprises a floating point unit which comprises standard...
6463451 High speed digital signal processor  
A digital signal processor being capable of rapidly operating a number of complex arithmetic formulae as such FFT. The digital signal processor operates data from first input line and data from...
6401194 Execution unit for processing a data stream independently and in parallel  
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic...
6385634 Method for performing multiply-add operations on packed data  
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored...
6330660 Method and apparatus for saturated multiplication and accumulation in an application specific signal processor  
An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation...
6269384 Method and apparatus for rounding and normalizing results within a multiplier  
A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands...
6249798 Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit  
An apparatus, a processor, a computer system and a method may be used to directly transfer and translate data between a memory format in an integer processing unit and a floating point format in a...
6230180 Digital signal processor configuration including multiplying units coupled to plural accumlators for enhanced parallel mac processing  
The present invention generally relates to multiply-accumulate units for use in digital signal processors. Each multiply-accumulate unit includes a multiply unit which is coupled with two or more...
6188240 Programmable function block  
A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group...
6065112 Microprocessor with arithmetic processing units and arithmetic execution unit  
Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the...
6061521 Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional...
6052705 Video signal processor with triple port memory  
A digital video signal processor using parallel processing includes an input serial-access memory having memory cells in which data is inputted into successive ones of the memory cells in response...
6006316 Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction  
A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle...
5991785 Determining an extremum value and its index in an array using a dual-accumulation processor  
A data processor determines an overall extremum value of an input set of array data, with the input set of array data partitionable into a first set of array data and a second set of array data....
5963461 Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization  
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are...
5941941 Bit width controlling method  
In the case that the bit width of a high-speed internal calculation of CPU or DSP is restricted and the high-speed internal calculation is performed as a fixed-point calculation, and the bit width...
5815420 Microprocessor arithmetic logic unit using multiple number representations  
A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical...
5805486 Moderately coupled floating point and integer units  
A moderately coupled floating point and integer units of a processor allows for rapid transfer of data between the two units. The integer unit is comprised of a plurality of integer registers...
5703800 Signal processor  
An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided...
5689450 Parallel processor  
A parallel processor for processing a plurality of pieces of data includes a number of unitary processing units provided in parallel equal to the number of pieces of data. Each of the unitary...
5636154 Digital operation unit  
A digital operation unit includes a dual-port arithmetic logic unit (ALU) receiving data from a data bus and a plurality of registers selectively storing ALU computations. The digital operation...
5623434 Structure and method of using an arithmetic and logic unit for carry propagation stage of a multiplier  
A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data...
5594679 Adaptive video signal processing apparatus  
A processing apparatus which adaptively performs image compensation and encoding/expansion and decoding processing such as discrete cosine transformation (DCT)/inverse discrete cosine...
5566102 Arithmetic element coupling network  
An arithmetic element coupling network for inputting at least one signal to obtain a desired output includes a plurality of arithmetic elements including at least one of a first arithmetic element...
5560039 Apparatus and method for a four address arithmetic unit  
An instruction execution unit having an instruction format with four addresses. Two of the addresses may be defined as sources for operands. Two of the four addresses may be defined as a...
5532938 Numerical arithmetic processing unit  
Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data...
5530889 Hierarchical structure processor having at least one sub-sequencer for executing basic instructions of a macro instruction  
A hierarchical structure processor including a memory for storing processing instruction code data described sequentially; a main CPU for fetching and decoding the processing instruction code data...
5517436 Digital signal processor for audio applications  
A digital signal processor for efficiently handling audio applications is disclosed. The single chip digital signal processor includes an on-chip instruction memory for outputting instructions...
5507000 Sharing of register stack by two execution units in a central processor  
In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the...
5465225 Method of increasing the data-processing speed of a signal processor  
An apparatus and method increase the data-processing speed of a signal processor whose signal-processing unit includes at least one arithmetic logic unit and one multiplier which are fed with input...
5450607 Unified floating point and integer datapath for a RISC processor  
A 64-bit wide unified integer and floating-point datapath for a RISC processor. The unified datapath allows for the sharing of some of the major hardware resources within the integer and...
Matches 1 - 50 out of 83 1 2 >