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7624138 Method and apparatus for efficient integer transform  
A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment,...
7596472 Device for synthesis of a composite digital signal with explicit control of the first three moments thereof  
The device determines the weighting coefficients to be applied to N digital source signals to form a composite signal. The first- to third-order moments of the composite signal must respectively...
7567997 Applications of cascading DSP slices  
In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each...
7516307 Processor for computing a packed sum of absolute differences and packed multiply-add  
A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to...
7480690 Arithmetic circuit with multiplexed addend inputs  
Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports...
7472155 Programmable logic device with cascading DSP slices  
Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand...
7467175 Programmable logic device with pipelined DSP slices  
Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments...
7437401 Multiplier-accumulator block mode splitting  
A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and...
7428566 Multipurpose functional unit with multiply-add and format conversion pipeline  
A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic...
7353244 Dual-multiply-accumulator operation optimized for even and odd multisample calculations  
According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.
7231510 Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof  
A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue...
7225323 Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines  
A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic...
7216217 Programmable processor with group floating-point operations  
A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction...
7206927 Pipelined processor method and circuit with interleaving of iterative operations  
A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction...
7181484 Extended-precision accumulation of multiplier output  
A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move...
7142010 Programmable logic device including multipliers and configurations thereof to reduce resource utilization  
In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers....
7127482 Performance optimized approach for efficient downsampling operations  
An algorithm and hardware structure is described for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a...
7111166 Extending the range of computational fields of integers  
An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the...
7107305 Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions  
A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline...
7080113 Virtually parallel multiplier-accumulator  
A virtually parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a...
7043519 SIMD sum of product arithmetic method and circuit, and semiconductor integrated circuit device equipped with the SIMD sum of product arithmetic circuit  
In an SIMD sum of product arithmetic method of enabling a concurrent execution of 2n (where n is a natural number) parallel sum of product arithmetic (operations), the SIMD sum of product...
7043518 Method and system for performing parallel integer multiply accumulate operations on packed data  
A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation,...
7043517 Multiply accumulator for two N bit multipliers and an M bit addend  
A multiply accumulator performs a multiplication-and-addition operation for a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, wherein M is larger than 2N....
7035890 Apparatus for multiplying and accumulating numeric quantities  
An apparatus for multiplying and accumulating numeric quantities, including a multiplier for receiving the numeric quantities, with the multiplier having a sum output and a carry output. A first...
7027598 Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7027597 Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7013321 Methods and apparatus for performing parallel integer multiply accumulate operations  
According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand...
7010558 Data processor with enhanced instruction execution and method  
An apparatus and method for performing enhanced algorithmic processing, including reduced cycle-count fast Fourier transform (FFT) calculations. In one aspect, the invention comprises a...
6988184 Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations  
Methods of performing dyadic digital signal processing (DSP) instructions. In one embodiment of the invention, the method includes fetching a dyadic DSP instruction having a main operation and a...
6976049 Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options  
The present invention relates to a method and system for providing a single accumulatable packed multi-way addition instruction having the functionality of multiple instructions without causing any...
6957242 Noninterfering multiply-MAC (multiply accumulate) circuit  
A noninterfering multiply-MAC (multiply accumulate) circuit is described. The circuit is operational to perform a MAC (multiply accumulate) operation and to perform a multiply operation without...
6925480 Microarchitecture of an arithmetic unit  
The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an...
6857061 Method and apparatus for obtaining a scalar value directly from a vector register  
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
6854003 Video frame rendering engine  
A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal...
6820102 DSP unit for multi-level global accumulation  
In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The...
6795553 Method and apparatus for modular inversion for information security and recording medium with a program for implementing the method  
Values X and N of n bits and a parameter t are input, then Y=X2 −t mod N is calculated, then an extended binary GCD algorithm is executed for Y to obtain S=y −1 2 k mod N and k, and R=S2...
6792442 Signal processor and product-sum operating device for use therein with rounding function  
An object of the present invention is to provide a multiply-accumulate unit with a rounding function which is capable of effecting 16-bit multiply-accumulate operations taking into account the...
6784888 Method and apparatus for executing a predefined instruction set  
The occurrence of an (n+m) input operand instruction that requires more than n of its input operands from an n-output data source is recognized by a programmable vertex shader (PVS) controller. In...
6754542 Control arithmetic apparatus and method  
A control arithmetic device includes a subtracting section, disturbance application detecting section, error correction amount calculating section, error correction amount convergence calculating...
6745219 Arithmetic unit using stochastic data processing  
Arithmetic unit having a set of multipliers and adders receives initial data in the form of both digital operands and analog signals. Stochastic multipliers and adders carry out multiplication and...
6732132 Digital signal processor and digital signal processing system incorporating same  
A digital signal processor (DSP) is disclosed which is capable of starting a new arithmetic operation even when results of completed arithmetic operations cannot be written into accumulators...
6728796 Arrangement and method for signal processing and storing  
A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a...
6658503 Parallel transfer size calculation and annulment determination in transfer controller with hub and ports  
The transfer controller with hub and ports originally developed as a communication hub between the various locations of a global memory map within the DSP is described. Using the technique of this...
6643768 Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder  
A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to...
6631461 Dyadic DSP instructions for digital signal processors  
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the...
6622153 Virtual parallel multiplier-accumulator  
A virtual parallel multiplier-accumulator (VMAC) that can execute more than or less than one MAC operation in a single system clock cycle. The inventive VMAC advantageously employs a...
6611856 Processing multiply-accumulate operations in a single cycle  
A multiply-accumulate unit, or MAC, may achieve high throughput. The MAC need not use redundant hardware, such as multiple Wallace trees, or pipelining logic, yet may perform Wallace tree and carry...
6609143 Method and apparatus for arithmetic operation  
It is an object of the present invention to provide an arithmetic logic unit that can perform a sum-of-products operation in a reduced number of processing cycles without carrying out data transfer...
6609142 Method of performing multiplication with accumulation in a Galois body  
A method is provided for performing multiplication with accumulation in a Galois Field on a first data, a second data, and a third data, with each of the data being coded on 2 n bits. A first...
6581086 Multiply and accumulate unit (MAC) and method therefor  
A multiply and accumulate (MAC) unit ( 52 ) having a multiplier ( 54 ) and an adder ( 56 ) for providing a calculated result of a MAC operation, an accumulator ( 58 ) for storing the calculated...
Matches 1 - 50 out of 141 1 2 3 >