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7609895 Methods and apparatus for performing MQ-decoding operations  
Methods and apparatus for providing JPEG decoder functions are described. In particular, features and methods of the present invention are directed to an efficient way of implementing a non-common...
7493357 Random carry-in for floating-point operations  
A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first...
7398289 Method and device for floating-point multiplication, and corresponding computer-program product  
In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial...
7330867 Method and device for floating-point multiplication, and corresponding computer-program product  
In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial...
7290024 Methods and apparatus for performing mathematical operations using scaled integers  
Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and...
7277540 Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography  
An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the...
7240204 Scalable and unified multiplication methods and apparatus  
Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2 m )) include...
7219117 Methods and systems for computing floating-point intervals  
Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is...
7188133 Floating point number storage method and floating point arithmetic device  
In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented...
7113593 Recursive cryptoaccelerator and recursive VHDL design of logic circuits  
A method and apparatus for performing cryptographic computations employing recursive algorithms to accelerate multiplication and squaring operations. Products and squares of long integer values are...
7111166 Extending the range of computational fields of integers  
An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the...
7027598 Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7027597 Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7003540 Floating point multiplier for delimited operands  
A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate...
6988120 Arithmetic unit and method thereof  
A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a...
6922714 Floating point unit power reduction scheme  
A system and method for reducing the power consumption of a floating point unit of a processor wherein the processor iteratively performs floating point calculations based upon one or more input...
6901503 Data processing circuits and interfaces  
An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit...
6779013 Floating point overflow and sign detection  
A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit...
6697833 Floating-point multiplier for de-normalized inputs  
A method is disclosed for efficiently multiplying de-normalized floating-point numbers without necessarily incurring additional delay over the multiplication of normalized numbers, wherein the...
6647404 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier  
A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is...
6606700 DSP with dual-mac processor and dual-mac coprocessor  
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The...
6490607 Shared FP and SIMD 3D multiplier  
A multiplier configured to perform multiplication of both scalar floating point values (X×Y) and packed floating point values (i.e., X 1 ×Y 1 and X 2 ×Y 2 ). In addition, the multiplier may be...
6370247 Hash value generating method and device, data encryption method and device, data decryption method and device  
Hash values, keys and cipher text which have a high degree of data scrambling are generated rapidly. When a message is sent, divisional data of the message are input, and injection extension...
6269385 Apparatus and method for performing rounding and addition in parallel in floating point multiplier  
An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced. The apparatus...
6269384 Method and apparatus for rounding and normalizing results within a multiplier  
A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands...
6233595 Fast multiplication of floating point values and integer powers of two  
A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand,...
6226737 Apparatus and method for single precision multiplication  
An apparatus and method for performing single precision multiplication in a microprocessor are provided. The apparatus includes translation logic and extended precision floating point execution...
6205462 Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously  
Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives...
6175907 Apparatus and method for fast square root calculation within a microprocessor  
An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a...
6099158 Apparatus and methods for execution of computer instructions  
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are...
6055554 Floating point binary quad word format multiply instruction unit  
An IEEE 754 standard floating point multiply instruction for binary extended precision format can be executed with a quad word format on an S/390 process. The multiplication calculation multiplies...
6032168 Computer system to perform a filter operation using a logarithm and inverse-logarithm converter and methods thereof  
In a parallel computer system having N parallel computing units a data pipeline connects all the computing units. In addition the computing units are coupled to a random access memory so that each...
6026483 Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands  
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product...
6021422 Partitioning of binary quad word format multiply instruction on S/390 processor  
There is a unique partitioning problem in determining how to execute the floating point multiply instruction defined by IEEE 754 standard for the quad word format on a S/390 processor. Several...
5999961 Parallel prefix operations in asynchronous processors  
A circuit for performing prefix computation in an asynchronous digital processor by implementing a serial process and a tree process for the same prefix computation in parallel. The first output...
5991784 Signal processing circuit  
A circuit for applying a predetermined algorithm to an input signal, has an input for receiving the input signal, a signal processing device for processing the input signal in accordance with the...
5963461 Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization  
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are...
5909385 Multiplying method and apparatus  
A multiplying apparatus includes a Booth decoder for performing a second-order Booth decode on a multiplier, a Booth selector for generating a partial product except the two high-order digits from...
5844827 Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N  
A method and apparatus in accordance with the present invention provides for multiplying and/or dividing an operand by 2 N using an arithmetic shifter where N is an integer represented in 2's...
5841684 Method and apparatus for computer implemented constant multiplication with multipliers having repeated patterns including shifting of replicas and patterns having at least two digit positions with non-zero values  
A method for designing a constant multiplier system comprises identifying a repeated pattern in a minimal signed digit expression of a multiplier, designing a first accumulator stage to compute the...
5790446 Floating point multiplier with reduced critical paths using delay matching techniques  
A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53×53...
5619439 Shared hardware for multiply, divide, and square root exponent calculation  
The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias...
5602769 Method and apparatus for partially supporting subnormal operands in floating point multiplication  
A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered...
5430668 Floating point multiplier capable of easily performing a failure detection test  
A floating point multiplier includes an exponential part adder for receiving and adding exponential parts of a multiplied value and a multiplying value and outputting an exponential addition...
5347481 Method and apparatus for multiplying denormalized binary floating point numbers without additional delay  
A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed...
5341319 Method and apparatus for controlling a rounding operation in a floating point multiplier circuit  
A floating point multiply of two n-bit operands creams a 2n-bit result, but ordinarily only n-bit precision is needed, so rounding is performed. Some rounding algorithms require the knowledge of...
5276634 Floating point data processing apparatus which simultaneously effects summation and rounding computations  
A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data...
5204829 Interleaving operations in a floating-point numeric processor  
A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and...
5195051 Computation of sign bit and sign extension in the partial products in a floating point multiplier unit  
An arithmetic logic for selectively multiplying either floating point numbers and unsigned integers or signed integers. A signed integer request signal has a first state indicating a floating point...
5153848 Floating point processor with internal free-running clock  
In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial...
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