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7595659 Logic cell array and bus system  
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for...
7543013 Multi-stage floating-point accumulator  
A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages....
7509366 Multiplier array processing system with enhanced utilization at lower precision  
A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the...
7499962 Enhanced fused multiply-add operation  
An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first...
7490119 High speed adder design for a multiply-add based floating point unit  
An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound...
7480690 Arithmetic circuit with multiplexed addend inputs  
Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports...
7461117 Floating point unit with fused multiply add and method for calculating a result with a floating point unit  
The invention proposes a Floating Point Unit ( 1 ) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic ( 2 ) which...
7451172 Handling denormal floating point operands when result must be normalized  
A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal...
7428566 Multipurpose functional unit with multiply-add and format conversion pipeline  
A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic...
7392274 Multi-function floating point arithmetic pipeline  
A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the...
7392273 High-sticky calculation in pipelined fused multiply/add circuitry  
Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic,...
7392270 Apparatus and method for reducing the latency of sum-addressed shifters  
The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is...
7346643 Processor with improved accuracy for multiply-add operations  
Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier...
7290023 High performance implementation of exponent adjustment in a floating point design  
A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value,...
7254698 Multifunction hexadecimal instructions  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
7240085 Faster shift value calculation using modified carry-lookahead adder  
Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input...
7225323 Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines  
A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic...
7225216 Method and system for a floating point multiply-accumulator  
Aspects for performing a multiply-accumulate operation on floating point numbers in a single clock cycle are described. These aspects include mantissa logic for combining a mantissa portion of...
7216139 Programmable logic device including multipliers and configurations thereof to reduce resource utilization  
In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers....
7194498 Higher radix multiplier with simplified partial product generator  
A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a...
7080111 Floating point multiply accumulator  
A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit...
7058830 Power saving in a floating point unit using a multiplier and aligner bypass  
The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the...
7027598 Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
7027597 Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits  
A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received...
6988184 Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations  
Methods of performing dyadic digital signal processing (DSP) instructions. In one embodiment of the invention, the method includes fetching a dyadic DSP instruction having a main operation and a...
6963894 Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation  
Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. Preferably, the prediction is “pessimistic” in that it...
6904446 Floating point multiplier/accumulator with reduced latency and method thereof  
A circuit ( 10 ) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from...
6895423 Apparatus and method of performing product-sum operation  
To perform a product-sum operation by adding third data to a product of first data and second data, a floating point multiplier first multiplies the first data by the second data, and a bit string...
6857061 Method and apparatus for obtaining a scalar value directly from a vector register  
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
6842765 Processor design for extended-precision arithmetic  
A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the...
6820106 Method and apparatus for improving the performance of a floating point multiplier accumulator  
A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the...
6813626 Method and apparatus for performing fused instructions by determining exponent differences  
A method of executing a fused instruction is disclosed. The method begins by performing several actions, which may be performed serially or in parallel. These include performing a floating point...
6784888 Method and apparatus for executing a predefined instruction set  
The occurrence of an (n+m) input operand instruction that requires more than n of its input operands from an n-output data source is recognized by a programmable vertex shader (PVS) controller. In...
6779008 Method and apparatus for binary leading zero counting with constant-biased result  
A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are...
6757813 Processor  
In a processor executing plural instructions simultaneously, writin-destination-register numbers of the plural instructions to be executed simultaneously are compared, and kinds of operations to be...
6751644 Method and apparatus for elimination of inherent carries  
A fused instruction datapath is disclosed. The fused instruction datapath may include a normalization unit, a floating point mutltiplier coupled to the normalization unit, and a mantissa alignment...
6701337 Floating-point calculator  
A floating-point calculator includes an exponent part calculator device which executes subtraction by sequentially combining exponents of a plurality of operands, and obtains subtraction result...
6697832 Floating-point processor with improved intermediate result handling  
Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier...
6643768 Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder  
A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to...
6631461 Dyadic DSP instructions for digital signal processors  
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the...
6631391 Parallel computer system and parallel computing method  
There is provided a parallel computer and a parallel computing method which allows high precision parallel calculation to be executed without requiring a hardware scale while maintaining high...
6615341 Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control  
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning...
6606700 DSP with dual-mac processor and dual-mac coprocessor  
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The...
6571266 Method for acquiring FMAC rounding parameters  
A floating-point multiply accumulate method acquiring a final mantissa result comprises comparing exponents of (A*B) and C. Transferring part of the C mantissa to a CHI register. Shifting any part...
6553120 Method for data decorrelation  
Method for the cryptography of data recorded on a medium usable by a computing unit in which the computing unit processes an input information x using a key for supplying an information F(x)...
6542916 Data processing apparatus and method for applying floating-point operations to first, second and third operands  
A data processing apparatus and method is provided for applying a floating-point multiply-accumulate operation to first, second and third operands. The apparatus comprises a multiplier for...
6542915 Floating point pipeline with a leading zeros anticipator circuit  
Presented is a “high-order” Leading Zeros Anticipator or LZA circuit and specifically a five-input LZA. The prior-art two-input LZA circuit is part of almost all high-performance floating-point...
6493817 Floating-point unit which utilizes standard MAC units for performing SIMD operations  
The present invention provides a method and apparatus for performing floating-point operations. The apparatus of the present invention comprises a floating point unit which comprises standard...
6480872 Floating-point and integer multiply-add and multiply-accumulate  
A method and a device including, in one embodiment, a multiply array and at least one adder to perform a floating-point multiplication followed by an addition when operands are in floating-point...
6446195 Dyadic operations instruction processor with configurable functional blocks  
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the...
Matches 1 - 50 out of 107 1 2 3 >