|
Match
|
Document |
Document Title |
|
|
7493357 |
Random carry-in for floating-point operations
A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first...
|
|
|
7346642 |
Arithmetic processor utilizing multi-table look up to obtain reciprocal operands
Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using...
|
|
|
7155471 |
Method and system for determining the correct rounding of a function
A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and...
|
|
|
7069289 |
Floating point unit for detecting and representing inexact computations without flags or traps
A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the...
|
|
|
7069288 |
Floating point system with improved support of interval arithmetic
Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One...
|
|
|
7062525 |
Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method
For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for...
|
|
|
7058830 |
Power saving in a floating point unit using a multiplier and aligner bypass
The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the...
|
|
|
7047272 |
Rounding mechanisms in processors
An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate...
|
|
|
7024052 |
Motion image decoding apparatus and method reducing error accumulation and hence image degradation
An Hadamard transform coding circuit changes a rounding method for each Hadamard transform block to prevent a rounding operation from providing an error biased in one direction, as seen in a...
|
|
|
7003539 |
Efficiently determining a floor for a floating-point number
An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction...
|
|
|
6996596 |
Floating-point processor with operating mode having improved accuracy and high performance
Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes...
|
|
|
6988120 |
Arithmetic unit and method thereof
A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a...
|
|
|
6970897 |
Self-timed transmission system and method for processing multiple data sets
A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto...
|
|
|
6898614 |
Round-off algorithm without bias for 2's complement data
A round off mechanism maintains a mean value of the operand while rounding twos complement binary data. Positive data values are incremented at the first discard bit prior to truncation of the...
|
|
|
6889242 |
Rounding operations in computer processor
Various methods for performing rounding operations in a computer processor are described. A machine instruction sets the rounding mode, which is automatically applied to subsequent machine...
|
|
|
6820106 |
Method and apparatus for improving the performance of a floating point multiplier accumulator
A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the...
|
|
|
6804354 |
Cryptographic isolator using multiplication
A stream cipher cryptosystem includes a pseudo-random bit generator receiving a key and providing a vulnerable keystream vulnerable to crytanalysis, and a non-linear filter cryptographic isolator...
|
|
|
6760036 |
Extended precision visual system
A method for extending the data width of a graphics processing channel in a computer graphics system. The method includes the first step of providing a plurality of graphics processing channels...
|
|
|
6721772 |
Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls
For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant...
|
|
|
6684232 |
Method and predictor for streamlining execution of convert-to-integer operations
During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign,...
|
|
|
6668268 |
Method and apparatus for compiling dependent subtraction operations on arithmetic intervals
One embodiment of the present invention provides a system for compiling computer code to perform a subtraction operation between a first interval and a third interval to produce a resulting...
|
|
|
6615228 |
Selection based rounding system and method for floating point operations
A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital...
|
|
|
6571264 |
Floating-point arithmetic device
A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the...
|
|
|
6560623 |
Method and apparatus for producing correctly rounded values of functions using double precision operands
A method and apparatus for finding the hard-to-round double precision operands x when processed by a function f(x)and using these hard-to-round numbers to optimize f(x) hardware and software f(x)...
|
|
|
6535898 |
Fast floating-point truncation to integer form
A processor representation of a floating-point data item is converted to a representation of a truncated integer item, without changing the rounding mode of a processor. When the current rounding...
|
|
|
6510446 |
Floating point calculation method and unit efficiently representing floating point data as integer and semiconductor integrated circuit device provided with the same
A floating point calculation method according to the present invention includes steps of: receiving input data; performing calculation for data for an exponent portion of the input data for...
|
|
|
6493738 |
Apparatus and method for rounding numerical values according to significant digits or rounding interval
There is disclosed a method and apparatus for rounding numerals according to the number of significant digits or a rounding interval. The method starts with entering a numerical value x to be...
|
|
|
6427203 |
Accurate high speed digital signal processor
An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions...
|
|
|
6427160 |
Method and system for testing floating point logic
In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and...
|
|
|
6405231 |
Method and apparatus for rounding intermediate normalized mantissas within a floating-point processor
An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point...
|
|
|
6401107 |
Method and processor for reducing computational error in a processor having no rounding support
In a chain of linear time-invariant operations ( 401 ), all bias introduced between operations collectively produce a total deterministic error at the final output of the chain of operations ( 401...
|
|
|
6397238 |
Method and apparatus for rounding in a multiplier
A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands...
|
|
|
6366942 |
Method and apparatus for rounding floating point results in a digital processing system
A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided...
|
|
|
6356927 |
System and method for floating-point computation
A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines...
|
|
|
6314442 |
Floating-point arithmetic unit which specifies a least significant bit to be incremented
An object is to obtain a floating-point arithmetic unit with improved throughput. The floating-point arithmetic unit comprises a mantissa adder-subtracter portion (MAP) for performing arithmetic...
|
|
|
6292815 |
Data conversion between floating point packed format and integer scalar format
A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of...
|
|
|
6269385 |
Apparatus and method for performing rounding and addition in parallel in floating point multiplier
An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced. The apparatus...
|
|
|
6269384 |
Method and apparatus for rounding and normalizing results within a multiplier
A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands...
|
|
|
6263420 |
Digital signal processor particularly suited for decoding digital audio
A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical...
|
|
|
6233672 |
Piping rounding mode bits with floating point instructions to eliminate serialization
A floating point unit is provided which conveys the rounding mode in effect upon dispatch of a particular instruction with that particular instruction into the execution pipeline of the floating...
|
|
|
6219684 |
Optimized rounding in underflow handlers
The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding...
|
|
|
6205461 |
Floating point arithmetic logic unit leading zero count using fast approximate rounding
A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit...
|
|
|
6185593 |
Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations
The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for...
|
|
|
6175847 |
Shifting for parallel normalization and rounding technique for floating point arithmetic operations
The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is...
|
|
|
6173299 |
Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations
The present invention describes an apparatus and method to select the format of the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization...
|
|
|
6151615 |
Method and apparatus for formatting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations
The present invention describes an apparatus and method that formats the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and...
|
|
|
6148314 |
Round increment in an adder circuit
A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to...
|
|
|
6134574 |
Method and apparatus for achieving higher frequencies of exactly rounded results
A multiplier configured to obtain higher frequencies of exactly rounded results by adding an adjustment constant to intermediate products generated during iterative multiplication operations is...
|
|
|
6122651 |
Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions
Disclosed is a method and circuit for executing an overshifted rotate through carry instruction. The circuit and method generates an n-bit output operand and output carry flag which represents a...
|
|
|
6099158 |
Apparatus and methods for execution of computer instructions
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are...
|