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8095586 Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away  
Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other...
8069199 Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even  
Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other...
8005671 Systems and methods for dynamic normalization to reduce loss in precision for low-level signals  
A normalization factor for a current frame of a signal may be determined. The normalization factor may depend on an amplitude of the current frame of the signal. The normalization factor may also...
8005884 Relaxed remainder constraints with comparison rounding  
A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as...
8005885 Encoded rounding control to emulate directed rounding during arithmetic operations  
A processor, an instruction set architecture, an instruction, a computer readable medium and a method for implementing optimal per-instruction encoding of rounding control to emulate directed...
7948267 Efficient rounding circuits and methods in configurable integrated circuit devices  
A specialized processing block for a configurable integrated circuit device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The...
7949701 Method and system to perform shifting and rounding operations within a microprocessor  
A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An...
7765221 Normalization of a multi-dimensional set object  
Methods and apparatus, including computer systems and program products, for normalizing computer-represented collections of objects. A first minimum value can be normalized based on a second...
7752250 Rounding floating point division results  
A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or...
7730117 System and method for a floating point unit with feedback prior to normalization and rounding  
A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking...
7725519 Floating-point processor with selectable subprecision  
A floating-point processor with selectable subprecision includes a register configured to store a plurality of bits in a floating-point format, a controller, and a floating-point mathematical...
7720898 Apparatus and method for adjusting exponents of floating point numbers  
A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers,...
7720899 Arithmetic operation unit, information processing apparatus and arithmetic operation method  
An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an...
7659911 Method and apparatus for lossless and minimal-loss color conversion  
A method and apparatus for perfectly lossless and minimal-loss interconversion of digital color data between spectral color spaces (RGB) and perceptually based luma-chroma color spaces (Y′CBCR) i...
7493357 Random carry-in for floating-point operations  
A method and apparatus for adding and multiplying floating-point operands such that a fixed-size mantissa result is produced. In accordance with the present addition method, the mantissa of a first...
7346642 Arithmetic processor utilizing multi-table look up to obtain reciprocal operands  
Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using...
7155471 Method and system for determining the correct rounding of a function  
A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and...
7069289 Floating point unit for detecting and representing inexact computations without flags or traps  
A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the...
7069288 Floating point system with improved support of interval arithmetic  
Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One...
7062525 Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method  
For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for...
7058830 Power saving in a floating point unit using a multiplier and aligner bypass  
The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the...
7047272 Rounding mechanisms in processors  
An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate...
7024052 Motion image decoding apparatus and method reducing error accumulation and hence image degradation  
An Hadamard transform coding circuit changes a rounding method for each Hadamard transform block to prevent a rounding operation from providing an error biased in one direction, as seen in a...
7003539 Efficiently determining a floor for a floating-point number  
An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction...
6996596 Floating-point processor with operating mode having improved accuracy and high performance  
Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an oper...
6988120 Arithmetic unit and method thereof  
A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a...
6970897 Self-timed transmission system and method for processing multiple data sets  
A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto...
6898614 Round-off algorithm without bias for 2's complement data  
A round off mechanism maintains a mean value of the operand while rounding twos complement binary data. Positive data values are incremented at the first discard bit prior to truncation of the...
6889242 Rounding operations in computer processor  
Various methods for performing rounding operations in a computer processor are described. A machine instruction sets the rounding mode, which is automatically applied to subsequent machine...
6820106 Method and apparatus for improving the performance of a floating point multiplier accumulator  
A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the...
6804354 Cryptographic isolator using multiplication  
A stream cipher cryptosystem includes a pseudo-random bit generator receiving a key and providing a vulnerable keystream vulnerable to crytanalysis, and a non-linear filter cryptographic isolator...
6760036 Extended precision visual system  
A method for extending the data width of a graphics processing channel in a computer graphics system. The method includes the first step of providing a plurality of graphics processing channels...
6721772 Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls  
For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant...
6684232 Method and predictor for streamlining execution of convert-to-integer operations  
During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign,...
6668268 Method and apparatus for compiling dependent subtraction operations on arithmetic intervals  
One embodiment of the present invention provides a system for compiling computer code to perform a subtraction operation between a first interval and a third interval to produce a resulting...
6615228 Selection based rounding system and method for floating point operations  
A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital...
6571264 Floating-point arithmetic device  
A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the...
6560623 Method and apparatus for producing correctly rounded values of functions using double precision operands  
A method and apparatus for finding the hard-to-round double precision operands x when processed by a function f(x)and using these hard-to-round numbers to optimize f(x) hardware and software f(x)...
6535898 Fast floating-point truncation to integer form  
A processor representation of a floating-point data item is converted to a representation of a truncated integer item, without changing the rounding mode of a processor. When the current rounding...
6510446 Floating point calculation method and unit efficiently representing floating point data as integer and semiconductor integrated circuit device provided with the same  
A floating point calculation method according to the present invention includes steps of: receiving input data; performing calculation for data for an exponent portion of the input data for...
6493738 Apparatus and method for rounding numerical values according to significant digits or rounding interval  
There is disclosed a method and apparatus for rounding numerals according to the number of significant digits or a rounding interval. The method starts with entering a numerical value x to be...
6427203 Accurate high speed digital signal processor  
An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions...
6427160 Method and system for testing floating point logic  
In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and...
6405231 Method and apparatus for rounding intermediate normalized mantissas within a floating-point processor  
An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point...
6401107 Method and processor for reducing computational error in a processor having no rounding support  
In a chain of linear time-invariant operations (401), all bias introduced between operations collectively produce a total deterministic error at the final output of the chain of operations (401)....
6397238 Method and apparatus for rounding in a multiplier  
A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands...
6366942 Method and apparatus for rounding floating point results in a digital processing system  
A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided...
6356927 System and method for floating-point computation  
A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines...
6314442 Floating-point arithmetic unit which specifies a least significant bit to be incremented  
An object is to obtain a floating-point arithmetic unit with improved throughput. The floating-point arithmetic unit comprises a mantissa adder-subtracter portion (MAP) for performing arithmetic...
6292815 Data conversion between floating point packed format and integer scalar format  
A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of...
Matches 1 - 50 out of 119 1 2 3 >