Matches 51 - 100 out of 105 < 1 2 3 >
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6044392 Method and apparatus for performing rounding in a data processor  
A method and apparatus for performing rounding in a data processor (10). In one embodiment, two instructions are used to implement a procedure for rounding operands of finite but arbitrary...
5995992 Conditional truncation indicator control for a decimal numeric processor employing result truncation  
In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed,...
5954789 Quotient digit selection logic for floating point division/square root  
Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working...
5917741 Method and apparatus for performing floating-point rounding operations for multiple precisions using incrementers  
An integrated circuit and method for rounding a number in one of a first or second format to produce a rounded result wherein the number is represented by a set of bits. A first incrementer...
5909385 Multiplying method and apparatus  
A multiplying apparatus includes a Booth decoder for performing a second-order Booth decode on a multiplier, a Booth selector for generating a partial product except the two high-order digits from...
5886195 Thienyl compounds for inhibition of cell proliferative disorders  
The present invention relates to molecules capable of modulating tyrosine signal transduction to prevent and treat cell proliferative disorders or cell differentiation disorders associated with...
5880984 Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instruments  
A floating point arithmetic unit for performing independent multiply and add operations in the execution of a multiply-add instruction AC+B on three operands A, B, and C of p-bit precision includes...
5854758 Fast fourier transformation computing unit and a fast fourier transformation computation device  
To provide FFT computing units, FFT computation devices, and pulse counters that can achieve computational precision using the smallest possible circuit size. FFT computing unit 602 comprises a...
5841683 Least significant bit and guard bit extractor  
In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken...
5812439 Technique of incorporating floating point information into processor instructions  
A floating point system and method employing instructions where instruction have incorporated floating point information. The floating point information indicates whether an exception trap should...
5808926 Floating point addition methods and apparatus  
A floating point addition unit includes two subunits each of which performs the addition. One subunit ("rounding subunit") rounds the addition result, and the other subunit ("non-rounding subunit")...
5764555 Method and system of rounding for division or square root: eliminating remainder calculation  
A method and system which provides exactly rounded division and square root results for a designated rounding mode independently of a remainder, or equivalent calculation of the relationship...
5761103 Left and right justification of single precision mantissa in a double precision rounding unit  
A double precision rounding unit is employed for both single and double precision rounding. Rounding double precision mantissas employs the double precision rounding unit normally. For rounding...
5754458 Trailing bit anticipator  
A method and apparatus for determining the trailing bit position from a two operand addition is described. The determination of the trailing bit occurs in parallel with the addition. The two...
5748516 Floating point processing unit with forced arithmetic results  
Logic for selectively forcing arithmetic results allows a floating point unit to bypass the normal flow through arithmetic units and pipelines depending on the particular floating point operation...
5742537 Fast determination of floating point sticky bit from input operands  
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from...
5696711 Apparatus and method for performing variable precision floating point rounding operations  
An apparatus and method for performing variable precision floating point rounding operations is provided that accomplishes rounding of a number that is faster, less complex and requires less...
5696709 Program controlled rounding modes  
A computer system having a default floating point rounding mode that may be overridden by a rounding mode designated by an instruction. The current machine rounding mode is stored in a register,...
5694350 Rounding adder for floating point processor  
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from...
5627773 Floating point unit data path alignment  
A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from...
5568412 Rounding-off method and apparatus of floating point arithmetic apparatus for addition/subtraction  
An apparatus and method for arithmetic addition/subtraction of first and second floating point operands, each having a fraction portion and an exponent, includes an alignment circuit, an...
5550768 Rounding normalizer for floating point arithmetic operations  
A method and apparatus for parallel "normalize-round-normalize" floating point arithmetic. The rounding-normalizer of the invention receives as an input an infinitely precise mantissa which is the...
5548544 Method and apparatus for rounding the result of an arithmetic operation  
An apparatus for rounding an answer produced during the execution of an operation by a multiple stage execution pipeline includes first circuitry for detecting when the operation is iterative and...
5511016 Method for store rounding and circuit therefor  
A method and circuit for store rounding a number wherein the guard bit and least significant bit of the number are selectively exchanged depending on the IEEE rounding mode to simplify the...
5508948 Numeric representation converting apparatus and vector processor unit such apparatus  
A numeric representation converting apparatus comprises a weight determining circuit, a decimal alignment circuit, a converting circuit, and a selecting circuit. The weight determining circuit...
5469377 Floating point computing device for simplifying procedures accompanying addition or subtraction by detecting whether all of the bits of the digits of the mantissa are 0 or 1  
A floating point computing device having a mantissa register for storing a mantissa of a floating-point number, a detecting circuit for determining the bit states of the consecutive bits of the...
5430668 Floating point multiplier capable of easily performing a failure detection test  
A floating point multiplier includes an exponential part adder for receiving and adding exponential parts of a multiplied value and a multiplying value and outputting an exponential addition...
5390134 System and method for reducing latency in a floating point processor  
A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function...
5341319 Method and apparatus for controlling a rounding operation in a floating point multiplier circuit  
A floating point multiply of two n-bit operands creams a 2n-bit result, but ordinarily only n-bit precision is needed, so rounding is performed. Some rounding algorithms require the knowledge of...
5303175 Floating point arithmetic unit  
The number of zeroes in an operation result of 54 bits is counted by a priority encoder 2 on a three-bit basis. A 54×18 normalization shifter 3 normalizes the operation result in response to the...
5276634 Floating point data processing apparatus which simultaneously effects summation and rounding computations  
A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data...
5258943 Apparatus and method for rounding operands  
A microprocessor which includes means for rounding a 68 bit binary number. The rounding bit is calculated based on the precision, rounding mode, and the Guard, Round, and Sticky bits. One path...
5235533 Store rounding in a floating point unit  
Apparatus for converting to a single precision or double precision number an extended precision floating point number comprised of a sign field, an exponent field and a mantissa field. A sticky...
5222037 Floating-point processor for performing an arithmetic operation on fixed-point part data with high speed rounding of a result  
A floating-point processor includes a carry saving adder-subtracter for generating carry data and sum data by performing addition and subtraction of a first fixed-point part having a greater...
5212661 Apparatus for performing floating point arithmetic operation and rounding the result thereof  
An approximate solution Ya of a function F with respect to a given value X is derived by referring to a relation Y=F(X) at an accuracy at which an error between the approximate solution Ya and an...
5150319 Circuitry for rounding in a floating point multiplier  
A rounding circuit for a binary tree floating point multiplier including apparatus for providing the upper bits of a mantissa presuming that no carry-in has occurred without waiting for the...
5128889 Floating-point arithmetic apparatus with compensation for mantissa truncation  
A floating-point multiplication apparatus is described which includes circuits for predicting the logical sum of a set of low-significance bits which are truncated from an intermediate product...
5040138 Circuit for simultaneous arithmetic calculation and normalization estimation  
An arithemtic circuit (10) which comprises an adder/rounder circuit (20) and a normalization estimation circuit (24) coupled in parallel to operand register (14, 19). A signed digit subtracter (25)...
4977535 Method of computation of normalized numbers  
Floating point numbers are processed by an apparatus, where an increment step may be necessary on a number but where that number may or may not have to be normalized, depending on the computation....
4941120 Floating point normalization and rounding prediction circuit  
Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization...
4926370 Method and apparatus for processing postnormalization and rounding in parallel  
A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is...
4849923 Apparatus and method for execution of floating point operations  
In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The...
4839846 Apparatus for performing floating point arithmetic operations and rounding the result thereof  
An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an...
4796217 Rounding unit for use in arithmetic processing of floating point data  
A rounding unit for use in arithmetic processing of register floating point data. The rounding unit comprises a mantissa part register for storing the mantissa part of the floating point data, an...
4779220 Floating-point data rounding and normalizing circuit  
A floating-point data rounding and normalizing circuit comprises a shift controller receiving a fraction portion of an input floating-point data for generating a shift control signal indicative of...
4758972 Precision rounding in a floating point arithmetic unit  
A floating point computation unit having an arithmetic unit employing two guard digits for preserving information needed for rounding and an indicator generator for providing an indicator signal to...
4562553 Floating point arithmetic system and method with rounding anticipation  
A floating point arithmetic system with rounding anticipation including an arithmetic unit for arithmetically combining two mantissas; a carry circuit for determining whether the sum will overflow...
4468748 Floating point computation unit having means for rounding the floating point computation result  
A floating point computation unit for use in a data processing system in which the mantissa processing means provides an overall computation result a portion of which represents the desired...
4442498 Arithmetic unit for use in data processing systems  
A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting...
4386413 Method and apparatus of providing a result of a numerical calculation with the number of exact significant figures  
A method and a digital computer for providing the result of a calculation performed upon data having a floating point representation, with the number of exact significant figures in this result....
Matches 51 - 100 out of 105 < 1 2 3 >