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RE40883 Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision  
A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A...
7447725 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units  
An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control...
7222146 Method and apparatus for facilitating exception-free arithmetic in a computer system  
One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the...
7099851 Applying term consistency to an equality constrained interval global optimization problem  
One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q 1 (x)=0 (i=1, . . . , r), wherein...
7058830 Power saving in a floating point unit using a multiplier and aligner bypass  
The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the...
6981012 Method and circuit for normalization of floating point significants in a SIMD array MPP  
The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing...
6728739 Data calculating device and method for processing data in data block form  
A data calculating device preferably used to improve the calculation precision when fixed-point calculation is performed by block-floating-point system. Each piece of data of a data group is...
6578059 Methods and apparatus for controlling exponent range in floating-point calculations  
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main...
6557021 Rounding anticipator for floating point operations  
A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One...
6219684 Optimized rounding in underflow handlers  
The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding...
6138135 Propagating NaNs during high precision calculations using lesser precision hardware  
A floating point arithmetic unit provides consistent propagation of NaNs le performing high precision calculations on hardware designed to perform lower precision calculations. In one embodiment,...
6049865 Method and apparatus for implementing floating point projection instructions  
A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for...
5966085 Methods and apparatus for performing fast floating point operations  
A format for representing floating point numbers reduces the overhead typically associated with parsing floating point numbers and thereby provides for significantly improved processing speeds,...
5943249 Method and apparatus to perform pipelined denormalization of floating-point results  
A method of processing a floating-point instruction (including a multiply-add instruction) in a floating-point processor. Prior-art techniques require prenormalization of intermediate results...
5894428 Recursive digital filter  
A recursive digital filter has a recursive arithmetic operation circuit and an output compensation circuit. The output compensation circuit outputs a value of zero as output data of the recursive...
5892697 Method and apparatus for handling overflow and underflow in processing floating-point numbers  
A method for processing floating-point numbers, each floating-point number having at least sign portion, an exponent portion and a mantissa portion, comprising the steps of converting a...
5809292 Floating point for simid array machine  
A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein...
5805487 Method and system for fast determination of sticky and guard bits  
A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A...
5781464 Apparatus and method for incrementing floating-point numbers represented in diffrent precision modes  
An incrementer for performing floating-point calculations is capable of incrementing a floating-point number represented in one of several different precision modes. The incrementer includes...
5619711 Method and data processing system for arbitrary precision on numbers  
A data processing system 10 comprises an arbitrary precision number C++ class program code 18, which incorporates arbitrary precision arithmetic. The arbitrary precision number program code 18...
5408427 Detection of exponent underflow and overflow in a floating point adder  
An exponent subtractor system (226) for a floating point adder (200) generates an exponent result (EXP - - low) and a rounded exponent result (EXP - - high) for an addition operation performed on...
5309383 Floating-point division circuit  
A floating-point division circuit for performing division on floating-point data using a non-recovery type division method is disclosed. The floating-point division circuit includes a circuit...
5212662 Floating point arithmetic two cycle data flow  
A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle...
5197023 Hardware arrangement for floating-point addition and subtraction  
A hardware arrangement for executing floating-point execution of addition and subtraction is supplied with two floating-point numbers each of which includes an exponential, a fraction represented...
RE33629 Numeric data processor  
A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers,...
5027308 Circuit for adding/subtracting two floating point operands  
In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit...
4994996 Pipelined floating point adder for digital computer  
A system for subtracting two floating-point binary numbers in a pipelined floating-point adder/subtractor by aligning the two fractions for sustraction; arbitrarily designating the fraction of one...
4943940 Floating point add/subtract and multiplying assemblies sharing common normalization, rounding and exponential apparatus  
A fully combinatorial floating point arithmetic apparatus is provided comprising separate fully combinatorial add/subtract and multiply assemblies which share a common normalization, rounding and...
4800516 High speed floating-point unit  
In a floating point arithmetic unit, high speed computation is achieved by providing logic for determining whether operands of an instruction have a predetermined condition with respect to the...
4788655 Condition code producing system  
A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and...
4773035 Pipelined data processing system utilizing ideal floating point execution condition detection  
An instruction execution unit receives instructions and, in turn, provides a sequence of control words to specify the sequential processing of the operand data provided with the instruction. A...
4649508 Floating-point arithmetic operation system  
In a floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, the operands X and Y are each...
4366548 Adder for exponent arithmetic  
A characteristic adder for use in a data processing system that performs floating-point arithmetic operations is described. A 1's complement subtractive adder is shown for forming the sum or...
Matches 1 - 33 out of 33