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7475103 Efficient check node message transform approximation for LDPC decoder  
In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and...
7461116 Emulation of a fixed point operation using a corresponding floating point operation  
A computer is programmed to emulate a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point...
7448026 Method and apparatus for accuracy-aware analysis  
A method for accuracy-aware analysis of a program involving obtaining source code for the program comprising a floating point variable, instrumenting the source code to associate an accuracy-aware...
7430656 System and method of converting data formats and communicating between execution units  
A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural...
7406589 Processor having efficient function estimate instructions  
High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different...
7397399 Method and device for transcoding N-bit words into M-bit words with M smaller N  
The present invention concerns a method for transcoding a N bits word into a M bits word with M<N. The invention is applicable in various fields and more particularly in the display field. The...
7395296 Circuitry and method for performing non-arithmetic operations  
Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to...
7389499 Method and apparatus for automatically converting numeric data to a processor efficient format for performing arithmetic operations  
A compiler (or interpreter) detects source language instructions performing arithmetic operations using a fixed point format (preferably packed decimal). Where the operation can be performed...
7373489 Apparatus and method for floating-point exception prediction and recovery  
An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of...
7330864 System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations  
A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction...
7321914 Fast method for calculating powers of two as a floating point data type  
A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment...
7299170 Method and apparatus for the emulation of high precision floating point instructions  
A high precision floating point emulator and associated method for emulating subject program code on a target machine where the subject machine base operands possess a different precision than the...
7236999 Methods and systems for computing the quotient of floating-point intervals  
Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a...
7228324 Circuit for selectively providing maximum or minimum of a pair of floating point operands  
A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point...
7219117 Methods and systems for computing floating-point intervals  
Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is...
7212959 Method and apparatus for accumulating floating point values  
A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained....
7191202 Comparator unit for comparing values of floating point operands  
A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to...
7133890 Total order comparator unit for comparing values of two floating point operands  
A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the...
7113969 Formatting denormal numbers for processing in a pipelined floating point unit  
A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one...
7099851 Applying term consistency to an equality constrained interval global optimization problem  
One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q 1 (x)=0 (i=1, . . . , r), wherein...
7069289 Floating point unit for detecting and representing inexact computations without flags or traps  
A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the...
7069288 Floating point system with improved support of interval arithmetic  
Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One...
7058830 Power saving in a floating point unit using a multiplier and aligner bypass  
The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the...
7054898 Elimination of end-around-carry critical path in floating point add/subtract execution unit  
A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in...
7051060 Operand conversion optimization  
According to the invention, optimization of an application by elimination of redundant operand conversions is disclosed. According to one embodiment, the optimization comprises receiving an...
7016928 Floating point status information testing circuit  
A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point...
6996596 Floating-point processor with operating mode having improved accuracy and high performance  
Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes...
6993549 System and method for performing gloating point operations involving extended exponents  
An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent...
6990505 Method/apparatus for conversion of higher order bits of 64-bit integer to floating point using 53-bit adder hardware  
A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an...
6976050 System and method for extracting the high part of a floating point operand  
A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an...
6970897 Self-timed transmission system and method for processing multiple data sets  
A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto...
6963895 Floating point pipeline method and circuit for fast inverse square root calculations  
Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and...
6922771 Vector floating point unit  
The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor...
6912557 Math coprocessor  
A math coprocessor 1300 includes a multiply-accumulate unit 1600 . Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the...
6904543 Electronic control having floating-point data check function  
An engine control ECU includes a microcomputer, which includes CPU, RAM, ROM, FPU and I/O. The FPU performs floating-point calculations and the CPU carries out operations other than the...
6904446 Floating point multiplier/accumulator with reduced latency and method thereof  
A circuit ( 10 ) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from...
6898615 Signal processing unit and signal processing method including using an exponent part and a mantissa part for power generation  
An exponent part extraction section extracts a bit series from the exponent part of an inputted floating point data. A mantissa part extraction section extracts the uppermost K bits from the...
6847378 System and method for performing scale and bias operations by preclamping input image data  
In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value...
6842765 Processor design for extended-precision arithmetic  
A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the...
6842764 Minimum and maximum operations to facilitate interval multiplication and/or interval division  
One embodiment of the present invention provides a system for performing a minimum/maximum computation for an interval operation. The system operates by receiving at least four floating-point...
6801924 Formatting denormal numbers for processing in a pipelined floating point unit  
A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one...
6789098 Method, data processing system and computer program for comparing floating point numbers  
The present invention provides a method, data processing system and computer program for comparing first and second floating point numbers involving providing a hierarchy of tests arranged to...
6754688 Method and apparatus to calculate the difference of two numbers  
An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the...
6732134 Handler for floating-point denormalized numbers  
Operations that involve denormalized numbers are handled by restructuring the input values for an operation as normalized numbers, and performing calculations on the normalized numbers. As a first...
6683530 Method and apparatus for performing a floating point compare operation  
A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is...
6671796 Converting an arbitrary fixed point value to a floating point value  
A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an...
6658443 Method and apparatus for representing arithmetic intervals within a computer system  
One embodiment of the present invention provides a system for representing intervals within a computer system to facilitate efficient and sharp arithmetic interval operations. The system operates...
6647401 High speed emulation of arithmetic operations  
A method of executing arithmetic operations in a data processing apparatus wherein first and second numbers having a main frame “e-mode format are converted to IEEE double format. Arithmetic...
6631391 Parallel computer system and parallel computing method  
There is provided a parallel computer and a parallel computing method which allows high precision parallel calculation to be executed without requiring a hardware scale while maintaining high...
6615341 Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control  
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning...
Matches 1 - 50 out of 159 1 2 3 4 >