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6606097 |
Circuit for generating frame buffer values
A floating point to fixed point converter suitable for determining values for an n-bit frame buffer of a graphics adapter is disclosed. The converter includes a floating point unit that receives a...
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6601079 |
Converting between different floating point exponent representations
A method for distinguishing an ordinary binary floating point number from an extraordinary binary floating point number is provided, the method including adding 1 to a B-bit biased exponent of a...
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6591361 |
Method and apparatus for converting data into different ordinal types
A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central...
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6571264 |
Floating-point arithmetic device
A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the...
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6529928 |
Floating-point adder performing floating-point and integer operations
An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for...
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6519694 |
System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity
In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the...
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6516332 |
Floating point number data processing means
The floating point number data processing means is for use in microprocessor systems and finds application in AC motor drive technology. The format used includes a sign bit, a seven bit signed...
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6502117 |
Data manipulation instruction for enhancing value and efficiency of complex arithmetic
A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction,...
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6484251 |
Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor
A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky...
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6425074 |
Method and apparatus for rapid execution of FCOM and FSTSW
A microprocessor configured to rapidly execute floating point store status word (FSTSW) type instructions that are immediately preceded by floating point compare (FCOM) type instructions is...
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6412065 |
Status register associated with MMX register file for tracking writes
A portion of an x86 microprocessor that supports MMX instructions provides a write tracking unit that tracks writes to a separately provided MMX register file, and updates a status register...
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6397239 |
Floating point addition pipeline including extreme value, comparison and accumulate functions
A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far...
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6393452 |
Method and apparatus for performing load bypasses in a floating-point unit
The present invention provides a method and apparatus for performing load bypasses with data conversion in a floating-point unit. This process of reading instructions and data out of a cache memory...
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6388586 |
Method for reversing the bits of a computer data structure
The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed...
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6317824 |
Method and apparatus for performing integer operations in response to a result of a floating point operation
A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and...
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6301594 |
Method and apparatus for high-speed exponent adjustment and exception generation for normalization of floating-point numbers
A method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1)...
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6298365 |
Method and system for bounds comparator
The invention relates to a method of using a "bounds" comparator scheme and to a "bounds" comparator circuit. The method of using this scheme or comparator circuit allows a quick and easy test to...
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6253222 |
Compression of limited range floating point numbers
A high-speed method for the compression and decompression of floating point numbers. The floating point numbers are biased using a predefined value and then stored in compressed format occupying...
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6240431 |
Decompression of limited range floating point numbers
A high-speed method for the compression and decompression of floating point numbers. The floating point numbers are biased using a predefined value and then stored in compressed format occupying...
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6212539 |
Methods and apparatus for handling and storing bi-endian words in a floating-point processor
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main...
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6212627 |
System for converting packed integer data into packed floating point data in reduced time
A method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. In one embodiment, a method includes moving the first...
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6205460 |
System and method for floating-computation for numbers in delimited floating point representation
Floating point numbers and other values are represented in a "delimited" representation in which all numbers, including those which would in the IEEE Std. 754 representation, be in the...
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6195672 |
Saturation detection in floating point to integer conversions
An improved method and apparatus for saturation detection in floating point to integer conversions is described. A floating point number is tested for saturation conditions based on an integer...
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6189094 |
Recirculating register file
A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values...
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6182100 |
Method and system for performing a logarithmic estimation within a data processing system
A method for performing a logarithmic estimation on a positive floating-point number within a data processing system is disclosed. A floating-point number includes a sign bit, multiple exponent...
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6178435 |
Method and system for performing a power of two estimation within a data processing system
A method for performing a power of two estimation on a floating-point number within a data processing system is disclosed. The floating-point number includes a sign bit, multiple exponent bits, and...
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6170001 |
System for transfering format data from format register to memory wherein format data indicating the distribution of single or double precision data type in the register bank
A data processing apparatus and method is provided, wherein in a first mode of operation, data of a first data type is processed, and in a second mode of operation, data of a second data type...
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6151669 |
Methods and apparatus for efficient control of floating-point status register
A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main...
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6148316 |
Floating point unit equipped also to perform integer addition as well as floating point to integer conversion
An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU...
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6144977 |
Circuit and method of converting a floating point number to a programmable fixed point number
A programmable numeric converter (10) converts a floating point number to a fixed point format by selecting the proper offset. The mantissa is loaded with an implied value one into the least...
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6141670 |
Apparatus and method useful for evaluating periodic functions
A computer and a method of using the computer to reduce an original argument to obtain a periodic function of the argument. A special number P j is employed that is close to a nontrivial...
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6122651 |
Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions
Disclosed is a method and circuit for executing an overshifted rotate through carry instruction. The circuit and method generates an n-bit output operand and output carry flag which represents a...
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6105047 |
Method and apparatus for trading performance for precision when processing denormal numbers in a computer system
An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by...
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6073155 |
Floating-point accumulator
To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is...
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6028893 |
Method and signal evaluation apparatus for data reduction in the processing of signal values with a digital processing unit in a transmission system
A signal evaluation apparatus, and method, for data reduction in the processing of signal values of a digital signal processing unit, for example, in a mobile communication system, wherein a block...
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6029243 |
Floating-point processor with operand-format precision greater than execution precision
A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double...
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6009511 |
Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers
A superscalar microprocessor appends a tag value to each floating point number. The tag value indicates whether the corresponding floating point number is a normal floating point number or a...
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5996056 |
Apparatus for reducing a computational result to the range boundaries of a signed 8-bit integer in case of overflow
An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are...
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5995122 |
Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format
A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit...
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5995991 |
Floating point architecture with tagged operands
A method for representing arithmetic values on which arithmetic operations can be performed uses operands having a fixed number of bits. In a first step, a plurality of operands are stored in a...
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5978901 |
Floating point and multimedia unit with data type reclassification capability
A superscalar microprocessor includes a combination floating point and multimedia unit. The floating point and multimedia unit includes one set of registers. The multimedia core and floating point...
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5954789 |
Quotient digit selection logic for floating point division/square root
Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working...
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5940311 |
Immediate floating-point operand reformatting in a microprocessor
A microprocessor (5) having an on-chip floating-point unit, or FPU, (31) is disclosed. Snoop logic (37) is present in the integer pipeline to detect the presence of floating-point load...
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5918062 |
Microprocessor including an efficient implemention of an accumulate instruction
An execution unit configured to perform a plurality of arithmetic operations using the same set of operands. These operands include corresponding input vector values in each of a plurality of input...
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5889980 |
Mode independent support of format conversion instructions for hexadecimal and binary floating point processing
A computer system having multiple floating point modes and common instructions for each mode in order to implement operations in a mode independent manner. A computer system includes two floating...
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5887160 |
Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor
A microprocessor synchronously executes instructions, the instructions including integer instructions for performing integer operations and floating point instructions for performing real number...
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5856831 |
Clamping system and method for clamping floating point color values from a geometry accelerator in a computer graphics system
A clamping system is designed to clamp floating point values from a geometry accelerator in a computer graphics system. The clamping system includes a register configured to receive the floating...
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5850346 |
System for embedding hidden source information in three-dimensional computer model data
In the subject invention, source information indicating an author, designer r other source of a three-dimensional computer model is embedded in the low-order digits or bits of floating point values...
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5848284 |
Method of transferring data between moderately coupled integer and floating point units
A moderately coupled floating point and integer units of a processor allows for rapid transfer of data between the two units. The integer unit is comprised of a plurality of integer registers...
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5844827 |
Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N
A method and apparatus in accordance with the present invention provides for multiplying and/or dividing an operand by 2 N using an arithmetic shifter where N is an integer represented in 2's...
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