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7562106 Multi-value digital calculating circuits, including multipliers  
Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and...
7543008 Apparatus and method for providing higher radix redundant digit lookup tables for recoding and compressing function values  
An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits...
7461107 Converter circuit for converting 1-redundant representation of an integer  
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive...
7433905 Device and method for processing digital values in particular in non-adjacent form  
A table establishes correspondence between first sets of at least one number, expressed in accordance with a signed code where each number may have the value of 0, 1 or −1, and second sets of at...
7296048 Semiconductor circuit for arithmetic processing and arithmetic processing method  
There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by...
7257609 Multiplier and shift device using signed digit representation  
The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware...
7213043 Sparce-redundant fixed point arithmetic modules  
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive...
7155474 Current-mode multi-valued full adder in semiconductor device  
A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a...
7099851 Applying term consistency to an equality constrained interval global optimization problem  
One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q 1 (x)=0 (i=1, . . . , r), wherein...
6816877 Apparatus for digital multiplication using redundant binary arithmetic  
A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k...
6728745 Semiconductor circuit for arithmetic operation and method of arithmetic operation  
There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by...
6671710 Methods of computing with digital multistate phase change materials  
Non-binary methods of computing utilizing a digital multistate phase change material. Addition, subtraction, multiplication, and division are accomplished with the controlled application of energy...
6567835 Method and apparatus for a 5:2 carry-save-adder (CSA)  
The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I 0 , I 1 , I 2 , I 3 and I 4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a...
6557021 Rounding anticipator for floating point operations  
A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One...
6546410 High-speed hexadecimal adding method and system  
Adder circuitry is provided based on a reduced mathematical method to provide high-speed hexadecimal addition. A first adder adds the least significant binary digits of two hexadecimal numbers to...
6347327 Method and apparatus for N-nary incrementor  
The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether...
6232894 Reproducible data conversion and/or compression method of digital signals and a data converter and a digital computer  
HEN2, which is a combination of signals in which at least one of two adjacent digits at any digit position of one or more digits of a 2-based three digit redundant binary number with one signal of...
6223199 Method and apparatus for an N-NARY HPG gate  
The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of...
6223195 Discrete cosine high-speed arithmetic unit and related arithmetic unit  
This arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in...
6219687 Method and apparatus for an N-nary Sum/HPG gate  
The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.
6216146 Method and apparatus for an N-nary adder gate  
The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.
6192387 Multiple resonant tunneling circuits for signed digit multivalued logic operations  
Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits....
6073149 Computational circuit  
A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and...
6047302 Memory storing redundant binary codes and arithmetic unit and discrete cosine transformer using such memory  
A memory, which consumes less electric power and has a longer life, stores a redundant binary code produced by replacing each digit of data in binary representation, with a separate 2-bit string...
5999962 Divider which iteratively multiplies divisor and dividend by multipliers generated from the divisors to compute the intermediate divisors and quotients  
A divider which multiplies both divisor and dividend by a first multiplier generated from the divisor to compute an intermediate divisor and an intermediate quotient, and iterates such computations...
5917742 Semiconductor arithmetic circuit  
A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data...
5822233 Digital arithmetic calculator and digital computer using non-redundant (2N+1) notation system with a radix of (2N+1)  
A central processing unit and a digital data processing system for performing arithmetic processing of numbers that are not presented using traditional 10 radix signed digits 0, 1, 2 . . . 9. The...
5815422 Computer-implemented multiplication with shifting of pattern-product partials  
A constant multiplication device is designed for multiplying a received binary multiplicand by a constant multiplier which, when expressed in binary or signed-digit notation, includes a repeated...
5815420 Microprocessor arithmetic logic unit using multiple number representations  
A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical...
5768476 Parallel multi-value neural networks  
In a parallel multi-value neural network having a main neural network 16 and a sub neural network 18 coupled with the main neural network 16 in parallel for an input signal, the main neural network...
5767476 Manufacturing method for automotive frame  
An automotive frame is assembled by joining fins of extrusions formed of aluminum alloy by resistance spot welding. The fins are formed integrally with each extrusion by extrusion. Alternatively,...
5680339 Method for rounding using redundant coded multiply result  
A data processing apparatus for rounding an input number coded in a redundant bit form including a magnitude signal and a sign signal for each bit of the input number. A carry path control signal...
5659495 Numeric processor including a multiply-add circuit for computing a succession of product sums using redundant values without conversion to nonredundant format  
A numeric processor includes a multiply-add circuit with redundant value interface circuitry for performing mathematical function computations as a succession of product sums using redundant binary...
5644522 Method, apparatus and system for multiply rounding using redundant coded multiply result  
A data processing apparatus for rounding an input number coded in a redundant bit form including a magnitude signal and a sign signal for each bit of the input number. A carry path control signal...
5574940 Data processor with quicker latch input timing of valid data  
A data processing apparatus includes a first data holding circuit, a second data holding circuit, a signal processing circuit, and a control circuit. The first data holding circuit outputs a signal...
5572455 Adder-subtractor device and method for making the same  
An adder-subtractor includes a jth device for each bit position j for computing a result for an expression ±a 0 ±a 1 , where a 0 and a 1 are binary numbers. The jth device is from a group of...
5570309 Iterative arithmetic processor  
A mantissa X Mk , which satisfies 1≤X Mk <2, is fed to a mantissa process section in order that the iterative multiplication operation of normalized floating-point numbers X k (k=0, . . . ,...
5524088 Multi-functional operating circuit providing capability of freely combining operating functions  
A multi-functional operating circuit provides a flexible architecture for dynamically or statically changing plural operating functions in a manner to complex the operating units needing the...
5483477 Multiplying circuit and microcomputer including the same  
A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the...
5469163 Multiple resonant tunneling circuits for positive digit range-4 base-2 to binary conversion  
Multiple resonant tunneling devices offer significant advantages for realizing circuits which efficiently convert values represented by multivalued number systems to conventional binary...
5467299 Divider and microcomputer including the same  
A subtraction-shift-type divider using a dividend or partial remainder represented by signed digits taking any of the values -1, 0, 1 and a divisor by twos complement representation. A selector,...
5467298 Multivalued adder having capability of sharing plural multivalued signals  
A multivalued adder for processing addition of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first input...
5463573 Multivalued subtracter having capability of sharing plural multivalued signals  
A multivalued subtractor for processing a multiplication of a first data and a second data, which are one of binary logic and multivalued logic, includes a first and second input circuit. The first...
5463572 Multi-nary and logic device  
An AND logic operation rule capable of carrying out an AND logic operation between binary digits and an AND logic operation between multi-nary digits is defined and an AND logic device utilizing...
5438533 Multivalued multiplier for binary and multivalued logic data  
A multivalued multiplier is arranged to treat a plurality of multivalued signals at one time without having to increase the circuit scale. The multivalued multiplier includes a logic circuit and a...
5416733 Apparatus for finding quotient in a digital system  
A fast divider is disclosed in the present invention. It utilizes a division method which uses a smaller quotient digit set of {-1, 1} than {-1, 0, 1} that used by known algorithms, therefore...
5398199 Many-valued logic processor for data query systems  
This data query apparatus consists of an application software and a circuitry for the processing of the data selection condition of the user query embodied in a host data base management system or...
5379244 Small-sized, low power consumption multiplication processing device with a rounding recoding circuit for performing high speed iterative multiplication  
A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is Υ, into consecutive N-digit sets (N is a natural...
5365471 Divider for performing signed division using a redundant signed digit  
A divider having a selector for selecting a numeral to be added to a dividend or partial remainder by an adder, which makes it possible to receive the numeral with a divisor reversing means, input...
5333117 Parallel MSD arithmetic using an opto-electronic shared content-addressable memory processor  
An opto-electronic shared content-addressable memory processor is used to perform parallel modified signed-digit (MSD) arithmetic operations. The MSD arithmetic operation (addition or subtraction...
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