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7558972 |
Data processing apparatus
A data processing apparatus comprises a plurality of calculating units connected each other in series, a plurality of memories connected in between the plurality of calculating units, and a control...
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7555692 |
End-to-end residue based protection of an execution pipeline
A processor that protects an execution pipeline includes a residue-based error detection infrastructure including a first logic for computing a first residue of a result of an executed instruction...
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7533294 |
Functional coverage driven test generation for validation of pipelined processors
A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the structure and behavior...
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7463678 |
Equalization scheme for DSL receivers in presence of an under-sampled or over-sampled transmit IDFT
A circuit and method is provided for reducing the effect of having potentially different sizes for an Inverse Discrete Fourier Transform (IDFT) at a transmitter and a Discrete Fourier Transform...
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7275125 |
Pipeline bit handling circuit and method for a bus bridge
A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a...
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7274369 |
Digital image compositing using a programmable graphics processor
Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a...
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7240082 |
Method for processing efficiency in a pipeline architecture
A method for improved processing efficiency of pipeline architecture with a processor. The processor has a first functional unit; a second functional unit; and a control unit electrically connected...
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7171535 |
Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline
A general-purpose serial operation pipeline realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. A plurality of...
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7107305 |
Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline...
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7047317 |
High performance network address processor system
A high performance network address processor is provided comprising a longest prefix match lookup engine for receiving a request for data from a designated network destination address. An...
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7043710 |
Method for early evaluation in micropipeline processors
A system and method for early evaluation in micropipeline processors to improve performance is provided. The present invention presents a design methodology where a micropipeline processor block...
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7007059 |
Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization
A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor...
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6870929 |
High throughput system for encryption and other data operations
According to one embodiment, an encryption system ( 500 ) includes an input buffer ( 504 ) that can provide data blocks from different contexts ( 522 - 1 to 522 -n) to a selected encryption...
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6813266 |
Pipelined access to address table in a network switch
A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined...
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6757819 |
Microprocessor with instructions for shifting data responsive to a signed count value
A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result...
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6745319 |
Microprocessor with instructions for shuffling and dealing data
A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand ( 600 ) and storing the shuffled result in a selected...
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6731644 |
Flexible DMA engine for packet header modification
A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive...
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6330631 |
Data alignment between buses
A bus bridge for a computer system for bridging first and second buses includes a shift and accumulate unit. The shift and accumulate unit includes a shifter having an input connected to receive...
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6192462 |
Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache
A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is...
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6185660 |
Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss
An apparatus in a computer, called a pending access queue, for providing data for register load instructions after a cache miss. After a cache miss, when data is available for a register load...
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6157751 |
Method and apparatus for interleaving a parallel image processing memory
A method and apparatus for accessing image pixel data in a plurality of parallel random access memories (RAMs) includes providing the RAMs so that they are arranged in pairs that each include an...
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6119048 |
Integrated circuit for processing digital signal
A digital signal process of a plurality of functions is enabled by a common hardware constructed on one chip having input terminals t1, t2 and t2'; output terminals t3 and t4; and a control signal...
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5944772 |
Combined adder and logic unit
A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the...
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5918042 |
Dynamic logic pipeline control
A multi-stage pipeline comprising a plurality of pipeline stages 2 is described. Each pipeline stage 2 incorporates a dynamic logic circuit 4, a latch circuit 6, and a pipeline stage control...
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5905881 |
Delayed state writes for an instruction processor
An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined...
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5848287 |
Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches
A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is...
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5787025 |
Method and system for performing arithmetic operations with single or double precision
A circuit for performing either single precision or double precision arithmetic operations on data, a system including such a circuit, and a method implemented by the system. Preferably, the...
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5764550 |
Arithmetic logic unit with improved critical path performance
An arithmetic logic unit (ALU) with improved critical path performance includes two sets of adder circuits, a logic circuit, a set of multiplexors and a decoder. The adder circuits perform...
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5426743 |
3-1 Arithmetic logic unit for simultaneous execution of an independent or dependent add/logic instruction pair
A high speed three-to-one data dependency collapsing ALU can be used to support multiple issue of instructions. The computing apparatus supports multiple issue of instructions it is useful in CISC,...
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5359718 |
Early scalable instruction set machine alu status prediction apparatus
An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic...
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5299319 |
High performance interlock collapsing SCISM ALU apparatus
Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of...
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5282153 |
Arithmetic logic unit
An arithmetic logic unit includes first and second buses for efficient operations upon multiple-bit operands. The arithmetic logic unit includes, in addition to the first and second buses, a shift...
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4876640 |
Logic controller having programmable logic "and" array using a programmable gray-code counter
A programmable logic device has a high level counter element and a programmable AND array suitable for control applications. Moore and Mealy state machines are readily implemented by the controller...
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4815021 |
Multifunction arithmetic logic unit circuit
A multifunction arithmetic logic circuit having comparison and numeric conversion circuitry, particularly adapted for use in graphics processing. The inventive architecture comprises a modular...
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4454589 |
Programmable arithmetic logic unit
A programmable arithmetic logic unit for performing high speed bit sliced, pipelined computations at very low power is fabricated as an LSI component using CMOS/SOS technology. It is...
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4051353 |
Accordion shift register and its application in the implementation of level sensitive logic system
Disclosed is a novel device, named the Accordion Shift Register (A.S.R.) by virtue of an alternative expansion-compaction behavior of the digital data as it passes through the device. The A.S.R....
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3631230 |
BINARY ARITHMETIC UNIT IMPLEMENTING A MULTIPLICATIVE STERATION FOR THE EXPONENTIAL, LOGARITHM, QUOTIENT AND SQUARE ROOT FUNCTIONS
Apparatus and a method is described for efficiently achieving arithmetic evaluations for functions such as exponential, logarithm, quotient, and square root with a minimum use of multiplications or...
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3474239 |
ADDER,SHIFTER AND LOGICAL APPARATUS
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