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7584233 |
System and method of counting leading zeros and counting leading ones in a digital signal processor
A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a...
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7477171 |
Binary-to-BCD conversion
Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.
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7467150 |
Block-aware encoding of bitmap for bitmap index eliminating max-slot restriction
Under block-aware encoding, a bitmap represented by atoms comprises a series of bitmaps for each data block in a database. Each bitmap in the series is referred to herein as a block bitmap. Each...
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7461110 |
Redundancy-free circuits for zero counters
A more efficient method of counting the number of zeros in a 4-bit value generates three output bits (q 0 , q 1 and q 2 ) from four input bits (a 0 , a 1 , a 2 and a 3 ) according to the logic...
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7430574 |
Efficient execution and emulation of bit scan operations
Methods are disclosed to implement bit scan operations using properties of two's complement arithmetic and compute zero index instructions. A data value may be provided and the most-significant or...
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7116663 |
Multi-field classification using enhanced masked matching
Methods and apparatus for finding a match between a target bit pattern and multiple filter bit patterns. A filter array is created from the filter bit patterns and at least one intermediate array...
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7096241 |
Exponent encoder circuit and mask circuit
In order to provide an exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code bits, there is provided a first logic circuit for...
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7024439 |
Leading Zero Anticipatory (LZA) algorithm and logic for high speed arithmetic units
Method and apparatus are described for anticipating the number of leading zeros or leading ones in a sum of mantissas irrespective of the sign of the result or the relative magnitudes of the input...
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6957238 |
Method and system for deterministic pseudo-random valid entry resolution
The present invention provides a method and system to select a valid entry in a deterministic pseudo-random approach. The method may randomly select one of numerous valid entries in order to ensure...
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6889235 |
Method and apparatus for quantifying the number of identical consecutive digits within a string
One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by...
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6779008 |
Method and apparatus for binary leading zero counting with constant-biased result
A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are...
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6760738 |
Exponent unit of data processing system
An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB)...
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6748406 |
Bit search device and bit search method
When one clock signal (CLK) is output, the following operations are performed: an input data signal D is latched by a data latch; a detection-type signal K is latched by a signal latch; the input...
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6697828 |
Optimized method and apparatus for parallel leading zero/one detection
A method and apparatus for detecting leading zeros in a number represented by a plurality of four-bit nibbles, each nibble having an associated order of significance, said method comprising is...
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6654776 |
Method and apparatus for computing parallel leading zero count with offset
A method and apparatus for computing leading zero count with offset (LZCO) using a parallel nibble calculation scheme. The invention receives as its input a first operand and a second “offset”...
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6654775 |
Optimized system and method for parallel leading one/zero anticipation
An optimized system and method for a parallel leading zero anticipation which ascertains “end of run” patterns in parallel. A string representing the operands of the floating-point addition is...
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6594679 |
Leading-zero anticipator having an independent sign bit determination module
A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a...
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6513053 |
Data processing circuit and method for determining the first and subsequent occurences of a predetermined value in a sequence of data bits
An apparatus and method is provided for determining locations of a predetermined value in a sequence of data bits. Each location is determined independently of the others thereby allowing them to...
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6499044 |
Leading zero/one anticipator for floating point
An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of...
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6477552 |
Device and method for performing a leading zero determination on an operand
A device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic...
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6385631 |
Priority encoder
A low voltage swing priority encoder comprising pass cells to provide differential voltages indicative of the leading one of a binary tuple. A tree structure with bypass paths allows for the...
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6381622 |
System and method of expediting bit scan instructions
A system and method of expediting bit scan instructions in a microprocessor is disclosed which employs an execution unit having zero detectors organized along predetermined boundaries for detecting...
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6369725 |
Method for binary to decimal conversion
An exemplary embodiment of the invention is a method and system for converting a number from binary to decimal. The method includes obtaining an N-bit binary number and then determining the number...
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6360238 |
Leading zero/one anticipator having an integrated sign selector
A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two...
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6205461 |
Floating point arithmetic logic unit leading zero count using fast approximate rounding
A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit...
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6195673 |
FOD (first-one-detector) circuit
A FOD (First-One-Detector) circuit for detecting the number of leading zeros counted from a most significant bit to a first one in a binary number includes a plurality of sub-FODs respectively...
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6173300 |
Method and circuit for determining leading or trailing zero count
A method and circuit for determining the position of a leading logical one or a trailing logical one in a first n bit operand is disclosed. The method and circuit generates an n bit operand from...
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6108747 |
Method and apparatus for cyclically searching a contents addressable memory array
To provide a method of searching a CAM which enables to search an address of matching contents cyclically recorded in a memory array of the CAM with a priority at once, the method of searching a...
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6108678 |
Method and apparatus to detect a floating point mantissa of all zeros or all ones
A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each...
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6085208 |
Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit
An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and...
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6058403 |
Broken stack priority encoder
A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a...
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6018757 |
Zero detect for binary difference
Zero detect of a difference of binary operands is disclosed. If the difference is zero, the bit-complement of the difference is a string of one's, and therefore incrementing the string of one's...
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5974432 |
On-the-fly one-hot encoding of leading zero count
A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of...
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5920493 |
Apparatus and method to determine a most significant bit
An adder using a leading zero/one detector (LZD) circuit and method of use determine an exact normalization shift with fewer logic levels and number of gates, resulting in saving considerable...
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5894427 |
Technique for concurrent detection of bit patterns
A technique for concurrently detecting a repetitive occurrence of a bit pattern in a bit string. Successive bits of the bit string are separated into bit groupings and the combined bits are...
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5889690 |
Multiply-add unit and data processing apparatus using it
A multiply-add unit includes a digit alignment shift number and exponent generator unit, an addend digit alignment and sign adjusting unit, a multiplier array, a sticky-bit for addend lower digits...
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5880978 |
Method and apparatus for creating an output vector from an input vector
A method for creating an output vector Z(n-1:0) from a first vector X(n-1:0) and a second vector Y(n-1:0). The second vector Y(n-1:0) is a complement of the first vector X(n-1:0). The method...
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5844826 |
Leading zero count circuit
A leading zero counter or anticipator is described herein which uses a 36-bit-wide bus. The bus can handle four 8 or 9-bit words, two 16-bit words, or one 32-bit word. The leading zero counter has...
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5831884 |
Apparatus for performing arithmetic operation of floating point numbers capable of improving speed of operation by performing canceling prediction operation in parallel
A leading zero anticipatory logic circuit generates a first result by AND operation of ith bit (i is an integer; 1≤i≤m) of a first mantissa and an ith bit of a second mantissa; generates a...
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5831877 |
Bit searching through 8, 16, or 32 bit operands using a 32 bit data path
A bit searching method shifts an operand and counts the number of shifts it takes to shift out the value one, thereby identifying the bit position in operand containing the value one. The operand...
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5798953 |
Apparatus and method for determining a number of digits leading a particular digit
When a data input signal having R plus X groups of M digits is received, the digits are segmented such that X different first counter-detectors receive M digits and a second counter-detector...
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5798952 |
Leading bit anticipator
Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as...
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5742621 |
Method for implementing an add-compare-select butterfly operation in a data processing system and instruction therefor
A parallel data structure and a dedicated Viterbi shift left instruction minimize the number of clock cycles required for decoding a convolutionally encoded signal in a data processing system (20)...
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5724275 |
Fast multi-operand bit pattern detection method and circuit
A process and associated apparatus for performing bit pattern detection, such as leading one detection and leading transition detection for early normalization of the result of an operation on...
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5721944 |
Method and system for implementing relative time discriminations in a high speed data transmission network
A data transmission network congestion control mechanism requires knowledge of the sequence of occurrence of two dates d1 and d2, respectively defined by times t1 and t2 provided by a wraparound...
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5708595 |
Efficient median filter and method therefor
An efficient method and apparatus of median filtering includes a memory circuit (305) for holding a list of N data samples (109). A grading circuit (309, 321, 313, 311) identifies a first data...
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5675617 |
Synchronous protocol encoding and decoding method
A method to encode and to decode frames of data used in synchronous protocols, including HDLC and SDLC. The invention operates on blocks of data, such as data bytes or data words, in a parallel...
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5657260 |
Priority detecting counter device
It is an object to measure the number of "zeros" standing from the head of an input bit string at a very high speed. A bit string D15-D0 of 16 bits is sequentially inputted to first blocks B7-B0 by...
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5592405 |
Multiple operations employing divided arithmetic logic unit and multiple flags register
A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a...
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5576982 |
Fast significant bit calculator and its application to integer multiplication and division
Disclosed is a Significant Bit Calculator (SBC) for determining the number of significant bits or nibbles of an operand in one clock period, and for using the result in performing binary arithmetic...
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