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7610472 |
Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option
Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The...
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7606848 |
Detector in parallel with a logic component
One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are...
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7548834 |
Method for processing sensor data
A method for processing sensor data which are transmitted by at least one asynchronous sensor at a transfer rate, the sensor data being read at a predefined sampling rate, a mean value being...
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7539715 |
Method and system for saturating a left shift result using a standard shifter
A method for left shifting data includes left shifting the data to produce a left-shift result, right shifting the data to produce a right-shift result, and determining if the left-shift result...
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7523019 |
Method for processing sensor data
A method for processing sensor data which are transmitted by at least one asynchronous sensor at a transfer rate into a buffer memory, the sensor data being read from the buffer memory at a...
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7480686 |
Method and apparatus for executing packed shift operations
A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory....
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7461109 |
Method and apparatus for providing packed shift operations in a processor
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch...
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7461108 |
Barrel shift device
When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a...
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7454089 |
Interpolation system and method
An interpolation system and method is applicable to image process of data size change. The characteristics of the interpolation system are that some simple operations in the system and method are...
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7409415 |
Processor system with efficient shift operations including EXTRACT operation
An electronic system ( 200 1 ) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and...
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7392270 |
Apparatus and method for reducing the latency of sum-addressed shifters
The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is...
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7349934 |
Processor system and method with combined data left and right shift operation
An integrated circuit device ( 100 ) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry for providing a second shift...
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7343388 |
Implementing crossbars and barrel shifters using multiplier-accumulator blocks
An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using...
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7340495 |
Superior misaligned memory load and copy using merge hardware
Method, apparatus, and program means for performing misaligned memory load and copy using aligned memory operations together with a SIMD merge instruction. The method of one embodiment comprises...
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7337202 |
Shift-and-negate unit within a fused multiply-adder circuit
A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift...
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7320013 |
Method and apparatus for aligning operands for a processor
A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a...
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7272622 |
Method and apparatus for parallel shift right merge of data
A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by...
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7231561 |
Apparatus and method for data pattern alignment
A digital tester includes a digital data pattern aligner. The digital data pattern aligner includes an alignment pattern source, a data shifter, and a data comparator. The alignment pattern source...
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7225212 |
Extended precision accumulator
A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move...
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7213129 |
Method and system for a two stage pipelined instruction decode and alignment using previous instruction length
A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for...
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7117232 |
Method and apparatus for providing packed shift operations in a processor
A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a...
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7035887 |
Apparatus and method for data shifting
A data shifter selects data from a plurality of data blocks to effectively “window” data contained within the blocks. A second stage of shifting may be implemented by selection among the...
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7030792 |
Suppressing digital-to-analog converter (DAC) error
A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC ( 640 and/or 645 ) that is part of a modulator (FIG. 6...
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6983297 |
Shifting an operand left or right while minimizing the number of multiplexor stages
A log shifter shifting an operand left or right while minimizing the number of multiplexor stages. The log shifter may contain a set of multiplexor stages, with at least one multiplexor stage...
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6978016 |
Circuits for calculating modular multiplicative inverse
The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in...
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6948014 |
Register for the parallel-serial conversion of data
Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers ( 2 ), each comprising series-connected data holding elements ( 3 ), each data holding...
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6934729 |
Method and system for performing shift operations
A method and an apparatus for performing a shift operation on an operand. The method and apparatus configures input lines to comprise a first part that includes the bits in order representing...
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6901503 |
Data processing circuits and interfaces
An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit...
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6901420 |
Method and apparatus for performing packed shift operations
A method and apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a...
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6901419 |
Arithmetic unit
The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital...
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6895424 |
Method and circuit for alignment of floating point significants in a SIMD array MPP
The processing elements of a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing...
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6895420 |
Apparatus and method for sharing data FET for a four-way multiplexer
Data sharing among adjacent logic gates for shifting data in a multiplexer. Each logic gate implements two stages of shifting and provides for data sharing by connecting data inputs among the logic...
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6877019 |
Barrel shifter
The present invention relates to a barrel shifter for manipulating bits within computer words. The barrel shifter includes multiple multiplexer stages for rotating single and multiple words. In...
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6865272 |
Executing permutations
A method for changing the bit-order of a data value in a data processing system having a register capable of storing data strings which each comprise a plurality of sub-strings that are not...
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6847378 |
System and method for performing scale and bias operations by preclamping input image data
In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value...
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6826584 |
Refinement of interpolated signals
A method including decimating a signal x using a filter f to obtain a decimated signal y, interpolating the decimated signal y to obtain a reconstructed signal z, determining a refinement factor s...
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6820186 |
System and method for building packets
Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory....
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6813657 |
Apparatus for processing a bit stream
A bit stream processing apparatus is provided which stores a bit stream in a circular buffer without separately storing a header and data of the bit stream. The bit stream processing apparatus...
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6785389 |
System for bitstream generation
A bitstream generator including a plurality of linear feed shift registers (LFSRs) operative to generate a bit stream and including: at least a first LFSR operative, when assigned as a generator...
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6779007 |
Wide shift array structure with low-voltage excursion sensing
A digital shifter apparatus features an n-bit wide shifter configured as a two-dimensional array of n 2 bit pass-through cells placed at substantially regular intervals within the array in n rows...
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6757819 |
Microprocessor with instructions for shifting data responsive to a signed count value
A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result...
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6754685 |
Dynamic popcount/shift circuit
A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The...
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6745216 |
Shift register allowing direct data insertion
A shift register allowing high-speed data insertion into a string of data with a relatively simple hardware-like configuration is disclosed. A plurality of register units connected in series, each...
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6738793 |
Processor capable of executing packed shift operations
An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input,...
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6715066 |
System and method for arranging bits of a data word in accordance with a mask
A system is described for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having...
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6675182 |
Method and apparatus for performing rotate operations using cascaded multiplexers
A method and apparatus performing rotate operations using cascaded multiplexers provides a scalable rotator circuit having a sub-field rotate capability that requires no additional interconnects at...
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6675181 |
Method and apparatus for determining a byte select vector for a crossbar shifter
A method and apparatus for determining a byte select vector for a crossbar shifter include processing that begins by storing data in a first set of byte locations and in a second set of byte...
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6654774 |
Generation of sign extended shifted numerical values
A computer-implemented method and system for performing an arithmetic shift right by n of an m-bit negative number. A right shifter executes a logical shift right operation on the number to be...
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6643673 |
Method and apparatus for arithmetic shifting
A method and apparatus for arithmetic shifting includes processing that begins by receiving a decoded instruction in a cycle of a pipeline process. Also during this cycle of the pipeline process,...
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6631389 |
Apparatus for performing packed shift operations
An apparatus for performing a shift operation on a packed data element having a multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second...
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