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7590673 Normalization at constant flow of a noise source for random number generation  
A method and a circuit for normalizing an initial bit flow, provided by a noise source, comprising dividing the bit flow into words of identical lengths, and assigning to each bit word of the...
7430656 System and method of converting data formats and communicating between execution units  
A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural...
7248700 Device and method for calculating a result of a modular exponentiation  
In a device for calculating a result of a modular exponentiation, the Chinese Residue Theorem (CRT) is used, wherein two auxiliary exponentiations are calculated using two auxiliary exponents and...
7096241 Exponent encoder circuit and mask circuit  
In order to provide an exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code bits, there is provided a first logic circuit for...
7086004 Generalized mechanism for unicode metadata  
A extendable method for including display rendering metadata within Unicode character streams. Metadata is distinct from character data, even though it is embedded in the Unicode character stream...
7062657 Methods and apparatus for hardware normalization and denormalization  
Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of...
6988115 Method and apparatus to correct leading one prediction  
A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one...
6981012 Method and circuit for normalization of floating point significants in a SIMD array MPP  
The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing...
6901503 Data processing circuits and interfaces  
An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit...
6779008 Method and apparatus for binary leading zero counting with constant-biased result  
A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are...
6765515 Arithmetic coding/decoding apparatus of MQ-Coder system and renormalization method  
In a renormalization processing device of MQ-CODER, the value of an augend register A is calculated by a shift quantity calculating unit without performing loop processing, and the number of left...
6760738 Exponent unit of data processing system  
An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB)...
6754688 Method and apparatus to calculate the difference of two numbers  
An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the...
6671796 Converting an arbitrary fixed point value to a floating point value  
A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an...
6622118 System and method for comparing signals  
A method and system that include a first measurement signal and a second measurement signal that can be input to first and second filters. The filters can be subject to a first constraint to...
6571264 Floating-point arithmetic device  
A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the...
6499044 Leading zero/one anticipator for floating point  
An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of...
6360238 Leading zero/one anticipator having an integrated sign selector  
A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two...
6301594 Method and apparatus for high-speed exponent adjustment and exception generation for normalization of floating-point numbers  
A method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1)...
6289366 Speedy shift apparatus for use in arithmetic unit  
An shift circuit is used in an arithmetic unit, for shifting m-bit input data to left or in right, m being a positive integer. The shift circuit includes a latch for temporarily storing the m-bit...
6219682 Vector normalizing apparatus  
A vector normalizing apparatus in which information concerning the norm of the original vector is not lost by normalization, and which needs no device that divides vector components by norm. The...
6185593 Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations  
The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for...
6178437 Method and apparatus for anticipating leading digits and normalization shift amounts in a floating-point processor  
A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and...
6175847 Shifting for parallel normalization and rounding technique for floating point arithmetic operations  
The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is...
6173300 Method and circuit for determining leading or trailing zero count  
A method and circuit for determining the position of a leading logical one or a trailing logical one in a first n bit operand is disclosed. The method and circuit generates an n bit operand from...
6173299 Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations  
The present invention describes an apparatus and method to select the format of the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization...
6154760 Instruction to normalize redundantly encoded floating point numbers  
The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an...
6108678 Method and apparatus to detect a floating point mantissa of all zeros or all ones  
A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each...
6101516 Normalization shift prediction independent of operand subtraction  
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from...
6085211 Logic circuit and floating-point arithmetic unit  
With the use of outputs of priority encoders serving as selection signals, final carry signals at respective bits in an adder can be selected as signals indicating whether or not prediction error...
6085208 Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit  
An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and...
6061749 Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword  
An apparatus for data normalization includes a FIFO buffer for receiving input data words, an input register for receiving a first data word from the FIFO buffer, and a combinatorial circuit for...
6018756 Reduced-latency floating-point pipeline using normalization shifts of both operands  
If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder...
5974432 On-the-fly one-hot encoding of leading zero count  
A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of...
5963461 Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization  
A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are...
5957997 Efficient floating point normalization mechanism  
A floating point result in a processor is efficiently normalized by predicting the mantissa shift required to normalize the result to an error of one bit position in one direction, resulting in...
5948049 Normalization circuitry  
Normalization circuitry comprises an AND gate for computing the AND of a reference signal generated from an exponent input with a mantissa input, and an OR gate for computing the OR of all the bits...
5931895 Floating-point arithmetic processing apparatus  
A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a...
5923575 Method for eletronically representing a number, adder circuit and computer system  
The invention relates to a method for electronically representing a number V in a binary data word. Both the exponent and the mantissa are represented as 2' complement. The mantissa is normalized...
5923574 Optimized, combined leading zeros counter and shifter  
By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for...
5920493 Apparatus and method to determine a most significant bit  
An adder using a leading zero/one detector (LZD) circuit and method of use determine an exact normalization shift with fewer logic levels and number of gates, resulting in saving considerable...
5903479 Method and system for executing denormalized numbers  
A method and system for processing instructions in a floating point unit for executing denormalized numbers in floating point pipeline via serializing uses an instruction unit and having a control...
5844827 Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N  
A method and apparatus in accordance with the present invention provides for multiplying and/or dividing an operand by 2 N using an arithmetic shifter where N is an integer represented in 2's...
5841683 Least significant bit and guard bit extractor  
In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken...
5808923 Denormalization device and method for multichannel audio decoder  
A device and a method for performing a denormalization operation to restore channel signals, normalized into specified levels due to a multichannel process in an MPEG-2 multichannel audio decoder,...
5798953 Apparatus and method for determining a number of digits leading a particular digit  
When a data input signal having R plus X groups of M digits is received, the digits are segmented such that X different first counter-detectors receive M digits and a second counter-detector...
5796644 Floating-point multiply-and-accumulate unit with classes for alignment and normalization  
A floating point multiply-and-accumulate unit that performs an operation A*B±C also determines an exponent difference (Ea+Eb)-Ec where Ea, Eb, and Ec are the exponents of values A, B, and C. The...
5790444 Fast alignment unit for multiply-add floating point unit  
A floating point arithmetic unit performs a multiply-add function B+(A*C) in which an alignment shifter is responsive to an input signal representative of the B mantissa. The shifter includes a...
5771183 Apparatus and method for computation of sticky bit in a multi-stage shifter used for floating point arithmetic  
Provided is a multi-stage shifter for use in both alignment and normalization shifters that provides faster implementation of the shifting process, requires less hardware and is less complex. One...
5764549 Fast floating point result alignment apparatus  
A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit...
Matches 1 - 50 out of 126 1 2 3 >