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7600206 Method of estimating the signal delay in a VLSI circuit  
A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI...
7596775 Method for determining a standard cell for IC design  
IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index)...
7596483 Determining timing of integrated circuits  
The present invention is directed to determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths....
7587691 Method and apparatus for facilitating variation-aware parasitic extraction  
One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which...
7581199 Use of state nodes for efficient simulation of large digital circuits at the transistor level  
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and...
7580037 Techniques for graphical analysis and manipulation of circuit timing requirements  
Techniques for organizing and displaying timing data derived from an EDA tool are provided that allows users to easily extract, analyze, and manipulate portions of the timing data relevant to...
7571412 Method and system for semiconductor device characterization pattern generation and analysis  
A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device...
7571398 Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits  
A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated...
7555689 Generating responses to patterns stimulating an electronic circuit with timing exception paths  
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that...
7555419 Simulation of system execution of instructions  
Instructions to be executed on a system are simulated. Representative simulation phases of the instructions, which most affect simulation results of the instructions to be executed on the system,...
7555417 Selectively reducing the number of cell evaluations in a hardware simulation  
An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the...
7552040 Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects  
A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times....
7546559 Method of optimization of clock gating in integrated circuit designs  
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for...
7542892 Reporting delay in modeling environments  
Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of...
7526745 Method for specification and integration of reusable IP constraints  
A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode...
7516383 Method and apparatus for analyzing delay in circuit, and computer product  
An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated...
7512918 Multimode delay analysis for simplifying integrated circuit design timing models  
A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc...
7506293 Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis  
A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected...
7500205 Skew reduction for generated clocks  
There is disclosed systems and processes for optimizing circuit descriptions by reducing clock skew, re-organizing and/or converting gated and generated clock circuits, and reconnecting clock nets...
7496491 Delay calculation method capable of calculating delay time with small margin of error  
A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor...
7487483 Clock model for formal verification of a digital circuit description  
The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the...
7487482 Method and system for evaluating a constraint of a sequential cell  
The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the...
7487475 Systems, methods, and apparatus to perform statistical static timing analysis  
A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit...
7487078 Method and system for modeling distributed time invariant systems  
A reduced order model of a distributed time invariant system is produced by projecting system matrices onto smaller matrices, interpolating the matrices and placing into a state-space system. The...
7484196 Method for asynchronous clock modeling in an integrated circuit simulation  
Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock...
7483823 Building integrated circuits using logical units  
Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models,...
7480607 Circuit design verification  
A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically...
7478346 Debugging system for gate level IC designs  
A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump...
7478030 Clock stabilization detection for hardware simulation  
Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common...
7478027 Systems, methods, and media for simulation of integrated hardware and software designs  
Systems, methods and media for simulation of integrated hardware and software designs are disclosed. More particularly, hardware and/or software for synchronizing cycle timers of an integrated...
7467366 Method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between components  
A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes...
7460984 Compensating for delay in modeling environments  
Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of...
7444607 Method for correcting timing error when designing semiconductor integrated circuit  
A method for correcting a timing error in an integrated circuit that includes a plurality of layout blocks with identical configurations in the same hierarchical layer. The method includes matching...
7444574 Stimulus extraction and sequence generation for an electric device under test  
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from...
7437696 Method and device for determining the time response of a digital circuit  
A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock...
7437695 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices  
A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy...
7424417 System and method for clock domain grouping using data path relationships  
A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains...
7421675 Annotating timing information for a circuit design for increased timing accuracy  
A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and...
7415404 Method and apparatus for generating a sequence of clock signals  
A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The...
7409329 Flexible SPDIF verification tool  
A system and method of verifying the format of a simulated signal produced during the simulation of an electronic circuit is disclosed. One aspect of the present invention includes a method of...
7403885 Voltage supply noise analysis  
Systems and methods for implementing voltage supply noise analysis for electronic circuits are disclosed. In an exemplary embodiment a computer program product executes a computer process. The...
7403884 Transient simulation using adaptive piecewise constant model  
A transient simulation system, methods and program product that implement an adaptive piecewise constant (PWC) model are disclosed. The invention evaluates an error criteria to determine a maximum...
7398445 Method and system for debug and test using replicated logic  
A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into...
7395519 Electronic-circuit analysis program, method, and apparatus for waveform analysis  
A design-change-target-circuit detecting unit inputs circuit information including an element model describing an electronic circuit to detect an electronic circuit using a changed element model. A...
7380228 Method of associating timing violations with critical structures in an integrated circuit design  
A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit...
7380226 Systems, methods, and apparatus to perform logic synthesis preserving high-level specification  
A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one...
7379855 Method and apparatus for timing modeling  
Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information...
7370302 Partitioning a large design across multiple devices  
A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality...
7366648 Electronic circuit analyzing apparatus, electronic circuit analyzing method, and electronic circuit analyzing program  
The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic...
7363610 Building integrated circuits using a common database  
Systems and methods for designing and generating integrated circuits using a high-level language are described. The high-level language is used to generate performance models, functional models,...
Matches 1 - 50 out of 295 1 2 3 4 5 6 >