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8185371 Modeling full and half cycle clock variability  
A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock...
8185369 Method and apparatus for characterizing properties of electronic devices depending on device parameters  
A system and method for obtaining information about an electronic device includes the steps of providing a criterion for a property of the electronic device depending on at least one device...
8185863 Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus  
A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect...
8176461 Design-specific performance specification based on a yield for programmable integrated circuits  
A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing...
8171442 Method and system to at least partially isolate nets  
A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the...
8165864 Method, system and computer program product for verifying address generation, interlocks and bypasses  
Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes...
8166432 Timing verification method and timing verification apparatus  
Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid...
8145967 System and method for verifying the receive path of an input/output component  
A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and...
8140316 Systems and methods for improving digital system simulation speed by clock phase gating  
An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the...
8131528 Reporting delay using visual indicators in a model  
Exemplary embodiments report delay incurred in a model. Exemplary embodiments identify an incurred delay that is related to a graphical affordance in the model and generate a visual indicator...
8132137 Prediction of dynamic current waveform and spectrum in a semiconductor device  
A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption...
8121827 Efficient presentation of functional coverage results  
Apparatus for presentation of functional coverage, including one or more processors and a memory, wherein the memory stores software instructions including instructions for representing a set of...
8086976 Methods for statistical slew propagation during block-based statistical static timing analysis  
Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and...
8082140 Parametric analysis of real time response guarantees on interacting software components  
A system and method for providing control timing for a vehicle system at the design level. The method includes defining component timing specifications in a parametric form at a system level and at...
8079006 Simulation method and computer-readable storage medium storing program for causing computer to analyze circuit operation using cell characteristics affected by environment  
A simulation method, to be implemented in a computer, carries out a simulation of a semiconductor integrated circuit. The simulation method carries out a layout analysis based on layout data of a...
8079013 Hardware description interface for a high-level modeling system  
A computer-implemented method of specifying a circuit design within a high-level modeling system (HLMS) can include, responsive to a scripted user input, instantiating a first and a second block...
8073670 Method for calculating delay time, program for calculating delay time and device for calculating delay time  
A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D2) (S4) for every circuit cell in a use condition range of a logic...
8073671 Dynamic software performance models  
Simulating an application. A method that may be practiced in a computing environment configured for simulating an application modeled by an application model deployed in a performance scenario of a...
8065090 Pairwise fragment interaction computation  
A method for creating a load balanced spatial partitioning of a structured, diffusing system of particles with pairwise interactions includes steps of: assigning a weight corresponding to a...
8065645 Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program  
A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means...
8060850 Method for designing semiconductor integrated circuit  
A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the...
8055483 System and method for performing hybrid expression evaluation  
A mechanism for evaluating hybrid expressions which allows access to more than one modeling domain is discussed. The present invention allows an evaluation of a portion of a hybrid expression in a...
8055494 Reporting delay in modeling environments  
Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of...
8051403 Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus  
A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect...
8046747 Apparatus and systems for measuring, monitoring, tracking and simulating enterprise communications and processes  
The present invention comprises apparatus and systems for measuring, monitoring, tracking and simulating enterprise communications and processes. A central message repository or database is...
8046725 Method of incremental statistical static timing analysis based on timing yield  
Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay...
8036873 Efficient clock models and their use in simulation  
Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled...
8028261 Method of predicting substrate current in high voltage device  
A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may...
8024683 Replicating timing data in static timing analysis operation  
An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least...
8019578 Simulation method of electromagnetic field and circuit analysis on first and second targets coupled together by a circuit element simulation apparatus, and computer-readable medium storing simulation program for performing the method  
A simulation apparatus according to an embodiment performs an electromagnetic field circuit coupling analysis on a first substrate and a second substrate electrically coupled via a circuit element...
8010933 Source synchronous timing extraction, cyclization and sampling  
A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the...
8010932 Structure for automated transistor tuning in an integrated circuit design  
A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant,...
8010923 Latch based optimization during implementation of circuit designs for programmable logic devices  
A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit...
8000951 Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof  
A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation...
7992122 Method of placing and routing for power optimization and timing closure  
A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one...
7987440 Method and system for efficient validation of clock skews during hierarchical static timing analysis  
A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the...
7983769 Time stamped motion control network protocol that enables balanced single cycle timing and utilization of dynamic data structures  
A system that enables controlling motion over a network comprises an interface that receives motion control data that includes a time stamp from the network. Additionally, the system includes a...
7983891 Receiver dependent selection of a worst-case timing event for static timing analysis  
A method for determining a worst-case transition is disclosed. The method includes determining a plurality of output slews for the plurality of input signals based on a timing model of a gate and...
7984354 Generating responses to patterns stimulating an electronic circuit with timing exception paths  
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that...
7979825 Method and system for the calculation of the sensitivities of an electrical parameter of an integrated circuit  
A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the...
7971169 System and method for reducing the generation of inconsequential violations resulting from timing analyses  
A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the...
7962870 Prediction of dynamic current waveform and spectrum in a semiconductor device  
A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design....
7949510 Distributed simultaneous simulation  
A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at...
7941775 Arbitrary waveform propagation through a logic gate using timing analysis results  
An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for...
7933761 Creation of clock and data simulation vectors with periodic jitter  
Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a...
7934187 Method and apparatus for performing electrical rule checks on a circuit design  
Method, apparatus, and computer readable medium for performing electrical rule checks (ERCs) on a circuit design are described. In one example, a hierarchy of cell instances is created from a...
7933747 Method and system for simulating dynamic behavior of a transistor  
Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the...
7930609 Apparatus and method for verifying target circuit  
A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second...
7930668 Placement and routing using inhibited overlap of expanded areas  
Methods of placing and routing a logic design are provided. The logic design includes logic elements and nets connecting the logic elements. A first placement and a partial routing of the logic...
7904286 Method and apparatus for scheduling test vectors in a multiple core integrated circuit  
A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test...
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