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7613599 |
Method and system for virtual prototyping
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are...
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7606698 |
Method and apparatus for sharing data between discrete clusters of processors
A method and apparatus for sharing data between processors within first and second discrete clusters of processors. The method comprises supplying a first amount of data from a first data array in...
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7600169 |
Systems and methods of test case generation with feedback
Systems and methods for implementing test case generation with feedback are disclosed. An exemplary system for test case generation with feedback comprises a plurality of knobs identifying test...
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7596483 |
Determining timing of integrated circuits
The present invention is directed to determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths....
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7587305 |
Transistor level verilog
A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a...
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7581199 |
Use of state nodes for efficient simulation of large digital circuits at the transistor level
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and...
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7574684 |
Design data creating method, design data creating apparatus and computer readable information recording medium
A design data creating method, for creating design data to which predetermined design constraint requirements are added, includes a display data converting step of converting input design...
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7571087 |
Computer storage exception handling apparatus and method for virtual hardware system
In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples,...
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7571086 |
Incremental circuit re-simulation system
A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter...
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7558722 |
Debug method for mismatches occurring during the simulation of scan patterns
A method and system are disclosed for testing for double shift errors in at least one scan chain of flip-flops during a simulation of the design of a digital integrated circuit chip. At the start...
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7555689 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths
Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit design having timing exception paths by more accurately determining the unknown values that...
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7555416 |
Efficient transistor-level circuit simulation
Techniques are described for performing analysis of circuits with nonlinear circuit components such as transistors based on a two-stage Newton-Raphson approach.
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7552043 |
Method, system and program product for selectively removing instrumentation logic from a simulation model
According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity...
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7546561 |
System and method of state point correspondence with constrained function determination
A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a...
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7536289 |
Method of configuring information processing system and semiconductor integrated circuit
A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step...
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7533011 |
Simulating and verifying signal glitching
A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals...
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7519525 |
Post initial microcode load co-simulation method, system, and program product
Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial...
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7519524 |
Program product for providing a configuration specification language supporting incompletely specified configuration entities
In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities...
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7516383 |
Method and apparatus for analyzing delay in circuit, and computer product
An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated...
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7512918 |
Multimode delay analysis for simplifying integrated circuit design timing models
A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc...
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7512912 |
Method and apparatus for solving constraints for word-level networks
The following techniques for word-level networks are presented: constraints solving, case-based learning and bit-slice solving. Generation of a word-level network to model a constraints problem is...
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7512531 |
Method and apparatus for specifying reactive systems
A method for specifying reactive systems using Dynamic State Machines (DSMs) is disclosed. The method extends statecharts in three areas. One is the integration of a group of related finite state...
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7509599 |
Method and apparatus for performing formal verification using data-flow graphs
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLM DFG and HLM DFG . RTLM DFG and HLM DFG are then put into...
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7506286 |
Method and system for debugging an electronic system
Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging...
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7506284 |
Event driven switch level simulation method and simulator
A method for simulating an integrated circuit includes performing a power supply voltage tuning operation to find a power supply voltage at which a simulation of the integrated circuit at an...
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7505887 |
Building a simulation of design block using a bus functional model and an HDL testbench
Methods and systems for building a simulation for verifying a design block, including efficient coordination of the control and validation of the operation of a first and second bus of the design...
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7502728 |
Code coverage testing in hardware emulation
Code coverage questions are addressed by a code coverage method that instruments an electronic module source design file with coverage probes and gives hierarchical names to the probes, then...
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7496820 |
Method and apparatus for generating test vectors for an integrated circuit under test
Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one...
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7493578 |
Correlation of data from design analysis tools with design blocks in a high-level modeling system
Methods are provided for processing design information of an electronic circuit design. A single path or multiple paths that are produced by a first design tool are an input for the method. Each...
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7493544 |
Extending test sequences to accepting states
State spaces are traversed to produce test cases, or test coverage. Test coverage is a test suite of sequences. Accepting states are defined. Expected costs are assigned to the test graph states....
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7484156 |
Apparatus and method for testing PS/2 interface
An apparatus for automatic testing of a PS/2 interface includes a micro controller unit, a PS/2 port, and a plurality of LEDs. The micro controller unit is coupled with both a data pin and a clock...
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7483824 |
Self-checking test generator for partially-modeled processors by propagating fuzzy states
A self-checking test generator program creates a self-checking test program that can test a device under test (DUT). The self-checking test generator selects instructions for a test. Selected...
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7480879 |
Substrate noise tool
System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse...
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7480608 |
Method and system for reducing storage requirements of simulation data via KEYWORD restrictions
Disclosed herein is a method of managing data results of simulation processing of a hardware description language (HDL) model based upon keywords. In accordance with the method, a restriction list...
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7480604 |
Method of modeling and producing an integrated circuit including at least one transistor and corresponding integrated circuit
A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing...
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7480602 |
System verification test using a behavior model
The present invention provides a system verification system that automatically generates a behavior model modeling the system under test in terms of actions of a test case and a range of expected...
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7478346 |
Debugging system for gate level IC designs
A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump...
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7478304 |
Apparatus for accelerating through-the-pins LBIST simulation
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a...
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7478029 |
Cable simulation device and method
A cable simulator that comprises an input device configured to receive a communication signal. The cable simulator further comprises a circuit configured to simulate attenuation in both the...
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7478028 |
Method for automatically searching for functional defects in a description of a circuit
A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional...
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7464287 |
Strategy to verify asynchronous links across chips
Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over...
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7464015 |
Method and apparatus for supporting verification, and computer product
In a verification supporting apparatus, when an obtaining unit obtains a verification scenario, a substituting unit substitutes an undefined value for a variable value in the verification scenario....
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7460988 |
Test emulator, test module emulator, and record medium storing program therein
There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test...
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7454325 |
Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases
According to one method of simulation processing, a count event counter for a count event is created within instrumentation of a hardware description language (HDL) simulation model of a design and...
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7454323 |
Method for creation of secure simulation models
Method and apparatus for security systems are provided to protect electronic designs from unauthorized usage. An obfuscation system is provided for creating secure simulation models of IP cores...
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7451426 |
Application specific configurable logic IP
An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level...
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7447966 |
Hardware verification scripting
Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification...
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7447620 |
Modeling asynchronous behavior from primary inputs and latches
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from...
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7444574 |
Stimulus extraction and sequence generation for an electric device under test
A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from...
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7444276 |
Hardware acceleration system for logic simulation using shift register as local cache
A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect...
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