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8439745 |
Electronic sweepstakes system providing multiple game presentations for revealing results from a single sweepstakes game
A system, apparatus, and method are disclosed wherein a reveal request is initiated through a result reveal station by a person (user) who has previously made some purchase or donation and has been...
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8443318 |
Method for modeling a magnetic tunnel junction with spin-polarized current writing
The junction comprising a stack of at least two magnetic layers, a first layer, for example a soft magnetic layer with controllable magnetization, and a second layer, for example a hard magnetic...
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8437988 |
Method and system for processing of threshold-crossing events
Methods, computer systems, and computer readable media are provided for simulation of a model of a system by detecting a violation of a cross condition while iteratively refining a first solution...
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8438519 |
Via-node-based electromigration rule-check methodology
A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit,...
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8438001 |
Method and apparatus for improving noise analysis performance
Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four...
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8438000 |
Dynamic generation of tests
Generation of a test based on a test template comprising of branch instructions. The test template may be a layout test template, defining a set of possible control flows possibilities between...
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8437870 |
System and method for implementing a virtual metrology advanced process control platform
System and method for implementing a VM APC platform are described. In one embodiment, the VM APC system comprises a process tool for processing a plurality of wafers, a metrology tool for...
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8438002 |
System and method of generating equation-level diagnostic error messages for use in circuit simulation
A mechanism for providing equation-level diagnostic error messages for system models undergoing circuit simulations is discussed. The components in a model of a system being simulated are converted...
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8433552 |
Circuit simulation method
A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a...
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8434032 |
Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design
The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for...
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8434045 |
System and method of providing a memory hierarchy
Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions...
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8428928 |
System and method for dynamically representing repetitive loads of a circuit during simulation
A system for dynamically representing repetitive loads of a circuit during simulation includes a simulator module having one or more computer programs for 1) identifying one or more driver circuits...
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8429594 |
Via design apparatus and via design method based on impedance calculations
A via design apparatus includes a determination section that determines a value of a shape parameter indicating a shape of a via in a multilayer board. The via has a hole passing through the...
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8429581 |
Method for verifying functional equivalence between a reference IC design and a modified version of the reference IC design
A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a...
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8429592 |
N/P configurable LDMOS subcircuit macro model
A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp...
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8423341 |
Method and system for constructing corner models for multiple performance targets
A method, system and article of manufacture are disclosed for constructing corner models for multiple performance targets for circuit simulations. The method includes identifying N (N≧2) p...
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8423879 |
Method and apparatus for test generation from hybrid diagrams with combined data flow and statechart notation
A test generator and methods for generating tests from a hybrid diagram are provided. A hybrid diagram is a diagram that primarily uses one higher-level semantic notation with portions utilizing...
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8423342 |
Simulation parameter extracting method of MOS transistor
A simulation parameter extracting method of a MOS transistor according to an exemplary aspect of the present invention includes evaluating a measured value that includes a true gate-overlap...
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8418094 |
Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit design
Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method...
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8417504 |
Conversion of circuit description to a transaction model
A system and method are described for converting a circuit description into transaction-based description at a higher level of abstraction. Thus, a designer can readily view a series of...
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8418098 |
Advisory system for verifying sensitive circuits in chip-design
A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits...
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8417503 |
System and method for target-based compact modeling
A method and structure for a computer model of a device has a performance parameter. The performance parameter includes a first bounded range and a second bounded range. The first bounded range has...
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8417505 |
System and method for simulating a transmission gate network and a bi-directional connect module within an analog and mixed-signal circuit
The present invention provides systems and methods for simulating an analog and mixed-signal circuit design comprising an analog circuit segment and a transmission gate network of a digital circuit...
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8413085 |
Digital netlist partitioning system for faster circuit reverse-engineering
Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry...
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8412497 |
Predicting simultaneous switching output noise of an integrated circuit
Predicting simultaneous switching output noise of an IC device is described. User input is obtained. The user input includes: an identification of an input/output bank of an integrated circuit die;...
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8412496 |
Simulation system, method, and program
A system, method and program to improve the processing speed of a simulation system. A processing system finds an entry point so that functional blocks cover a broad range. The processing system...
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8412507 |
Testing the compliance of a design with the synchronization requirements of a memory model
A method for compliance testing of a circuit design that includes at least one processor and a memory includes defining a memory model. The memory model includes synchronization mechanisms for...
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8407036 |
Method and apparatus for modeling the modal properties of optical waveguides
A method and apparatus models one or more electromagnetic field modes of a waveguide. The method includes calculating a first matrix having a plurality of elements and having a first bandwidth...
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8407636 |
Clock domain crossing verification support
A computer-readable, non-transitory medium stores therein a verification support program that causes a computer to execute a procedure. The procedure includes first detecting a state change in a...
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8402407 |
Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method
A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated...
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8401828 |
Methods and systems for analog object fetch in mixed-signal simulation
Systems and methods for simulating and verifying an analog mixed signal design provide an analog mixed signal testbench configured to verify analog parameters of the design. The testbench can...
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8402403 |
Verifying a register-transfer level design of an execution unit
A mechanism is provided for verifying a register-transfer level design of an execution unit. A set of instruction records associated with a test case are generated and stored in a buffer. For each...
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8402288 |
Apparatus and method for controlling voltage and frequency using multiple reference circuits
A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The method comprises: providing at least one reference circuit representative of a behavior...
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8396696 |
Using multiple processors to simulate electronic circuits
A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit...
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8397199 |
Versatile method and tool for simulation of aged transistors
In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified...
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8397190 |
Method for manipulating and repartitioning a hierarchical integrated circuit design
A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each...
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8396701 |
Software systems for development, control, programming, simulation, and emulation of fixed and reconfigurable lab-on-a-chip devices
A software system for development, control, programming, simulation, and emulation of fixed, software-configurable, software-reconfigurable, and software-controlled Lab-on-a-chip (“LoC”) dev...
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8390234 |
Method for the automated startup and/or for the automated operation of controllers of an electrical drive system with vibrational mechanics as well as an associated device
A method for automated startup and/or for automated operation of controllers of an electrical drive system with vibrational mechanics with the following steps: (a) determining a preliminary value...
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8392009 |
Advanced process control with novel sampling policy
The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a first plurality of semiconductor wafers; determining a sampling rate to the...
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8392859 |
Method and system for debugging using replicated logic and trigger logic
A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic...
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8392157 |
System synthesis to meet exergy loss target value
In a method of synthesizing components to design a system meeting an exergy loss target value, one or more candidate sets of components are synthesized and an exergy loss value for each of the one...
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8386229 |
Integrated circuit package component and ball grid array simulation model
A simulation model is provided for flip-chip BGAs to help engineers determine the effects of IC package components. The simulation model includes a bump model, a package planes model, a package...
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8386990 |
Unique identifier derived from an intrinsic characteristic of an integrated circuit
An embodiment of the invention relates to an integrated circuit such as an FPGA wherein a stable unique identifier is produced by reading an intrinsic characteristic of the IC such as a physically...
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8386974 |
Accelerating coverage convergence using symbolic properties
In a method for increasing coverage convergence during verification of a design for an integrated circuit, multiple simulation runs can be performed. Symbolic variables and symbolic expressions can...
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8380477 |
System of testing engineered safety feature instruments
The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is...
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8380476 |
Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties
Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the...
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8380480 |
Computer product, analysis support apparatus, and analysis support method
A non-transitory, computer-readable recording medium stores therein a program causing a computer to execute calculating, using respective standard deviations of first delay distributions of delay...
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8380478 |
Statistical evaluation of circuit robustness separating local and global variation
Semiconductor fabrication using statistical analysis (400) to determine the robustness or reliability of a fabricated integrated circuit module given global and local variations of operating...
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8380481 |
Conveying data from a hardware device to a circuit simulation
A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware...
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8380656 |
Technique for fast power estimation using probabilistic analysis of combinational logic
A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software...
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