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7618899 Method of patterning a matrix into a substrate via multiple, line-and-space, sacrificial, hard mask layers  
Methods of fabricating a semiconductor integrated circuit device are disclosed. The methods of fabricating a semiconductor integrated circuit device include forming a hard mask layer on a base...
7585784 System and method for reducing etch sequencing induced downstream dielectric defects in high volume semiconducting manufacturing  
A system and method is disclosed for reducing etch sequencing induced downstream dielectric defects produced in a SOG planarization process used in high volume semiconductor manufacturing. Three...
7585765 Formation of oxidation-resistant seed layer for interconnect applications  
An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a...
7582565 Method and apparatus for semiconductor wafer planarization  
Broadly speaking, the present invention provides a method and an apparatus for planarizing a semiconductor wafer (“wafer”). More specifically, the present invention provides for depositing a...
7576015 Methods for manufacturing alignment layer, active device array substrate and color filter substrate  
A method for manufacturing an alignment layer is provided, which includes the following steps. First, a substrate is provided. Next, an auxiliary layer is formed on the substrate. Then, an...
7553610 Method of forming fine patterns  
It is disclosed a method of forming fine patterns comprising: covering a substrate having photoresist patterns with an over-coating agent for forming fine patterns, applying heat treatment to cause...
7527188 Self-encapsulated silver alloys for interconnects  
Alloys of silver and an alloying element that diffuses to the surface of the high conductivity metal and is oxidizable to form an alloying element oxide such as beryllium are provided along with...
7482215 Self-aligned dual segment liner and method of manufacturing the same  
A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top...
7455955 Planarization method for multi-layer lithography processing  
The present invention is directed towards contact planarization methods that can be used to planarize substrate surfaces having a wide range of topographic feature densities for lithography...
7416985 Semiconductor device having a multilayer interconnection structure and fabrication method thereof  
A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench...
7384862 Method for fabricating semiconductor device and display device  
It is an object of the present invention to alleviate unevenness due to an opening for making a contact with the lower layer even when the opening has a large diameter (1 μm or more). Thus, it is...
7368393 Chemical oxide removal of plasma damaged SiCOH low k dielectrics  
A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged...
7297640 Method for reducing argon diffusion from high density plasma films  
A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used...
7282456 Self-repair and enhancement of nanostructures by liquification under guiding conditions  
In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the...
7270886 Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same  
A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a...
7235345 Agent for forming coating for narrowing patterns and method for forming fine pattern using the same  
It is disclosed an over-coating agent for forming fine patterns which is applied to cover a substrate having photoresist patterns thereon and allowed to shrink under heat so that the spacing...
7229914 Wiring layer structure for ferroelectric capacitor  
Wiring layers through that come into direct contact with an electrode of a ferroelectric capacitor provide a wiring layer structure configured so that the characteristic of the ferroelectric...
7208416 Method of treating a structured surface  
The invention provides a simple method of treating a structured surface comprising a higher surface in a first region and a lower surface in the second region. A plurality of layers is deposited on...
7199062 Method for forming a resist film on a substrate having non-uniform topography  
A preferred embodiment of the invention provides a method of spin coating a liquid, such as a resist, onto a surface of a substrate. An embodiment of the invention comprises dispensing a liquid...
7189659 Method for fabricating a semiconductor device  
A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32 a with a first pressure set in a deposition chamber; the step of gradually decreasing the...
7189499 Method of forming fine patterns  
It is disclosed a method of forming fine patterns comprising: covering a substrate having photoresist patterns with an over-coating agent for forming fine patterns, removing the unwanted...
7183172 Method of forming silicon-on-insulator (SOI) semiconductor substrate and SOI semiconductor substrate formed thereby  
A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI...
7157331 Ultraviolet blocking layer  
Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic...
7153731 Method of forming a field effect transistor with halo implant regions  
A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides...
7115468 Semiconductor device and method for fabricating the same  
A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the...
7087506 Method of forming freestanding semiconductor layer  
A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base...
7084079 Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications  
A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal...
7078296 Self-aligned trench MOSFETs and methods for making the same  
Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making...
7070659 System for filling openings in semiconductor products  
Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be formed of metal. The metal may be...
7060623 Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern  
A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper...
7060197 Micromechanical mass flow sensor and method for the production thereof  
In a mass flow sensor having a layered structure on the upper side of a silicon substrate ( 1 ), and having at least one heating element ( 8 ) patterned out of a conductive layer in the layered...
7041578 Method for reducing stress concentrations on a semiconductor wafer by surface laser treatment including the backside  
A method for treating an area of a semiconductor wafer surface with a laser for reducing stress concentrations is disclosed. The wafer treatment method discloses treating an area of a wafer surface...
6982217 Nano-structure and method of manufacturing nano-structure  
A structure having projections is provided. The structure having projections comprises a first projection formed on a first layer containing a first material, and a plurality of second projections...
6958298 Method for thinning wafer by grinding  
A method for thinning a wafer by placing a wafer having a protective tape attached to the front side thereof, on which chip circuits have been fabricated, on a working table in such a manner that...
6927160 Fabrication of copper-containing region such as electrical interconnect  
A copper-containing layer suitable for an electrical interconnect in a device such as an integrated circuit is created by a procedure in which a trench ( 104 ) is formed through a dielectric layer...
6926818 Method to enhance the adhesion between dry film and seed metal  
A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry...
6905980 Semiconductor device and method of manufacturing same  
A semiconductor device is produced by forming a gate oxide film on a silicon substrate, forming a gate electrode on the gate oxide film, forming a nitrogen-containing oxide film on the silicon...
6879046 Split barrier layer including nitrogen-containing portion and oxygen-containing portion  
A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can...
6878642 Method to improve passivation openings by reflow of photoresist to eliminate tape residue  
A new method to form passivation openings in the manufacture of an integrated circuit device is achieved. The passivation openings have gradually sloping sidewalls that allow a protective tape to...
6841472 Semiconductor device and method of fabricating the same  
A semiconductor device is provided with a semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film and having a...
6828254 Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same  
A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper...
6812113 Process for achieving intermetallic and/or intrametallic air isolation in an integrated circuit, and integrated circuit obtained  
The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the...
6803308 Method of forming a dual damascene pattern in a semiconductor device  
The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a...
6794310 Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof  
A method of determining temperature of a semiconductor wafer during wafer fabrication includes the step of providing a response circuit on the semiconductor wafer. The method also includes the step...
6773510 Substrate processing unit  
The present invention relates to a processing unit for processing a substrate, which comprises a chamber for housing the substrate and forming a hermetically closeable processing room, and an...
6743724 Planarization process for semiconductor substrates  
A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are...
6730619 Method of manufacturing insulating layer and semiconductor device including insulating layer  
A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an...
6723626 Method of manufacturing semiconductor device  
In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate, and a wiring line groove is formed in the insulating film. Then, a conductive film is...
6716767 Contact planarization materials that generate no volatile byproducts or residue during curing  
The present invention is directed towards planarization materials that produce little or no volatile byproducts during the hardening process when used in contact planarization processes. The...
6703321 Low thermal budget solution for PMD application using sacvd layer  
The present invention provides exemplary methods, apparatus and systems for planarizing an insulating layer, such as a borophosphosilicate glass (BPSG) layer, deposited over a substrate. In one...
Matches 1 - 50 out of 229 1 2 3 4 5 >