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6551930 Etching an organic material layer, particularly for producing interconnections of the damascene type  
A method for etching an organic dielectric material layer includes depositing an inorganic barrier layer on the organic dielectric material layer, and depositing an inorganic masking layer on the...
6551944 Process for manufacturing a semiconductor material wafer comprising single-Crystal regions separated by insulating material regions  
A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor...
6551941 Method of forming a notched silicon-containing gate structure  
A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate...
6537921 Vertical metal oxide silicon field effect semiconductor diodes  
The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high...
6534384 Method for manufacturing SOI wafer including heat treatment in an oxidizing atmosphere  
A method for manufacturing an SOI wafer. The method includes forming an oxide film on a surface of at least one silicon wafer of two silicon wafers. The method also includes bonding the silicon...
6530380 Method for selective oxide etching in pre-metal deposition  
A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as...
6531349 Method of etching polycrystalline silicon film by using two consecutive dry-etching processes  
A method for fabricating a semiconductor device including the steps of: sequentially forming an oxide film and a polycrystalline silicon film overlying a substrate; and selectively dry-etching the...
6531067 Method for forming contact hole  
The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level...
6527968 Two-stage self-cleaning silicon etch process  
A process for etching a substrate 25 in an etching chamber 105, and simultaneously removing etch residue deposited on the surfaces of the walls 110 and components of the etching chamber 105. In one...
6518192 Two etchant etch method  
A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as...
6513537 Substrate processing method and substrate processing apparatus  
The present invention relates to a method of removing a polymer veil and a metal contamination deposited on a substrate having a metal layer. First, the polymer veils are removed by a chemical...
6506680 Method of forming connections with low dielectric insulating layers  
In a semiconductor manufacturing method, etching control is provided by introducing a material containing a material having at least one of an —H, —C, —CH, —CH2, and —CH3 radical component...
6500745 Method for manufacturing sidewall spacers of a semiconductor device with high etch selectivity and minimized shaving  
A method for manufacturing a field effect transistor includes a first step for etching 70%˜90% of the thickness of an insulating film (SiO2 or Si3N4) formed covering a gate electrode formed on a ...
6500767 Method of etching semiconductor metallic layer  
A method of etching a metallic layer having an anti-reflection layer thereon. The method includes performing a first etching operation using a fixed set of processing parameters to etch the...
6492280 Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls  
A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density...
6489248 Method and apparatus for etch passivating and etching a substrate  
A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and...
6482728 Method for fabricating floating gate  
A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed...
6479396 Dry polymer and oxide veil removal for post etch cleaning  
In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical based processes that do not remove...
6479398 Method of manufacturing an amorphous-silicon thin film transistor  
A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and...
6475922 Hard mask process to control etch profiles in a gate stack  
A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack, minimizing the formation of micro-trenches while achieving nearly...
6472306 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer  
A method of forming a dual damascene opening, comprising the following steps. A semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over...
6468920 Method for manufacturing contact hole in semiconductor device  
A method for manufacturing a contact hole in a semiconductor device which includes the steps of preparing an active matrix provided with a substrate and word lines formed on the substrate, forming...
6464892 Methods of fabricating microelectromechanical and microfluidic devices  
Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The...
6458494 Etching method  
Etching method applicable to a semiconductor device fabrication and an MEMS(Micro-Electro-Mechanical System) process, including the steps of forming an etching mask on a substrate, forming a...
6458657 Method of fabricating gate  
A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different...
6453915 Post polycide gate etching cleaning method  
A method of cleaning polycide gates after an etching step. A gate oxide layer, a polysilicon layer, a titanium nitride layer, a silicide layer, an anti-reflection layer and a patterned photoresist...
6447688 Method for fabricating a stencil mask  
Disclosed is a novel method for fabricating a stencil mask comprising the formation of an absorber pattern, including an alignment key or target, on the topside of an SOI wafer having a transparent...
6446641 Method of manufacturing semiconductor device, and semiconductor device manufactured thereby  
There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer...
6444138 Method of fabricating microelectromechanical and microfluidic devices  
Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The...
6440869 Method of forming the capacitor with HSG in DRAM  
The present invention discloses the method of forming the bottom electrode with HSG (hemispherical grain) layer on substrate, said substrate comprising a word line and an active region, said method...
6440865 Method of profile control in metal etching  
A method of profile control in metal etching, wherein a metal layer is positioned on a dielectric layer comprising an aluminum-alloy layer on the dielectric and an anti-reflection layer on the...
6436612 Method for forming a protection device with slope laterals  
A method for forming a protection device with slope laterals is provided. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second...
6432806 Method of forming bumps and template used for forming bumps  
A method of manufacturing a template having through-holes for attracting and supporting electrically conductive balls by vacuum suction is disclosed. The through-holes are formed by etching and the...
6426299 Method and apparatus for manufacturing semiconductor device  
A second interlayer film is etched by an etching gas including fluorocarbon gas after a switch box is switched so that high frequency electricity is applied to an upper electrode. Then, the switch...
6426238 Charge transfer device and solid image pickup apparatus using the same  
A charge transfer device is provided, capable of preventing degradation of the charge transfer efficiency when the channel width becomes narrower due to the narrow channel effect. The charge...
6423618 Method of manufacturing trench gate structure  
A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base...
6420240 Method for reducing the step height of shallow trench isolation structures  
In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b)...
6417072 Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step  
The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the...
6417108 Semiconductor substrate and method of manufacturing the same  
A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor...
6410452 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device having a trench isolation structure includes patterning a mask film on a semiconductor substrate, forming a trench by etching the semiconductor...
6399505 Method and system for copper interconnect formation  
A system and method for reducing contamination in a semiconductor device formed on a substrate is disclosed. The method and system include providing a barrier metal layer on the substrate. A first...
6391792 Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer  
Within a method for forming an aperture fill layer within a aperture, there is first provided a topographic substrate having an aperture formed therein. There is then formed over the topographic...
6391749 Selective epitaxial growth method in semiconductor device  
A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial...
6387820 BC13/AR chemistry for metal overetching on a high density plasma etcher  
A method of manufacturing a semiconductor device by forming layers of materials on a semiconductor substrate and utilizing a series of etch chemistries to remove portions of the layers of materials...
6383923 Article comprising vertically nano-interconnected circuit devices and method for making the same  
A circuit device is disclosed comprising at least two circuit layers or circuit devices vertically interconnected with a plurality of parallel and substantially equi-length nanowires disposed...
6383945 High selectivity pad etch for thick topside stacks  
An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In...
6380078 Method for fabrication of damascene interconnects and related structures  
Method for fabrication of damascene interconnects and related structures is disclosed. A sacrificial layer is formed over a low-k dielectric. Trenches are then etched inside the sacrificial layer...
6368970 Semiconductor configuration and corresponding production process  
A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard...
6368979 Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure  
A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material...
6365509 Semiconductor manufacturing method using a dielectric photomask  
A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in...