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6645869 Etching back process to improve topographic planarization of a polysilicon layer  
An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover...
6642154 Method and apparatus for fabricating structures using chemically selective endpoint detection  
One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed...
6620560 Plasma treatment of low-k dielectric films to improve patterning  
Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG,...
6620686 Methods of forming capacitors having a polymer on a portion thereof that inhibits the formation of hemispherical grain (HSG) nodules on that portion and capacitors formed thereby  
A capacitor includes an electrode that has an inner surface, an outer surface, and an end surface. At least one of the inner surface and the outer surface has hemispherical grain (HSG) nodules...
6617085 Wet etch reduction of gate widths  
A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a...
6617249 Method for making thin film bulk acoustic resonators (FBARS) with different frequencies on a single substrate and apparatus embodying the method  
A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. An FBAR is fabricated on a substrate by...
6605546 Dual bake for BARC fill without voids  
A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating...
6605526 Wirebond passivation pad connection using heated capillary  
A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit...
6605547 Electrical standoff having a transmission structure and method of manufacture  
An electrical standoff has a dielectric substrate with opposing horizontal surfaces and at least two opposing vertical end walls. A transmission structure having planar elements is formed on the at...
6600231 Functional device unit and method of producing the same  
An implementation base (10) is formed of a silicon substrate (11) having a recess (12) on a surface. Wire layers (13) are formed on the silicon substrate (11), continuously extending from the...
6593235 Semiconductor device with a tapered hole formed using multiple layers with different etching rates  
A semiconductor device having an improved contact hole through an interlayer insulator. A first insulating film comprising silicon nitride is deposited. A second insulating film comprising silicon...
6589715 Process for depositing and developing a plasma polymerized organosilicon photoresist film  
A process for etching a PPMS layer that increases the etch selectivity of PPMS relative to PPMSO from an initial low etch selectivity to a higher etch selectivity at a later stage of the etching...
6589875 Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same  
In one illustrative embodiment, the method includes providing a wafer including at least one non-production area, forming a process layer above the wafer, forming a masking layer above the process...
6579806 Method of etching tungsten or tungsten nitride in semiconductor structures  
The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures. We have discovered a method of etching tungsten or tungsten nitride which permits...
6579809 In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric  
The invention provides a method of small geometry gate formation on the surface of a high-k gate dielectric wherein process complexity and processing costs are reduced while throughput and overall...
6576515 Method of forming transistor gate  
A method of forming a transistor gate. A substrate having a source/drain terminals, a gate dielectric layer, a lower section of a floating gate, a dielectric layer over the substrate is provided....
6576563 Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen  
The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate,...
6569777 Plasma etching method to form dual damascene with improved via profile  
A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer comprising a first feature opening anisotropically etched though a...
6566258 Bi-layer etch stop for inter-level via  
An inter-level metallization structure and the method of forming it, preferably based on copper dual damascene in which the lower-metal level is formed with a exposed metallization and an adjacent,...
6562416 Method of forming low resistance vias  
Low resistant vias are formed by sequentially treating an opening in an interlayer dielectric and the exposed surface of a lower metal feature with an NH3 plasma followed by a N2/H2 plasma, thereby...
6562723 Hybrid stack method for patterning source/drain areas  
A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack...
6559062 Method for avoiding notching in a semiconductor interconnect during a metal etching step  
A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in...
6555474 Method of forming a protective layer included in metal filled semiconductor features  
A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched...
6554002 Method for removing etching residues  
A method for removing fluorine-containing etching residues during dual damascene process comprises providing a dual damascene structure having a copper conductor structure therein, a cap layer...
6551942 Methods for etching tungsten stack structures  
The invention encompasses methods for etching and/or over-etching tungsten stack structures, especially tungsten-polysilicon stack structures. The etching methods of the invention preferably employ...
6551930 Etching an organic material layer, particularly for producing interconnections of the damascene type  
A method for etching an organic dielectric material layer includes depositing an inorganic barrier layer on the organic dielectric material layer, and depositing an inorganic masking layer on the...
6551944 Process for manufacturing a semiconductor material wafer comprising single-Crystal regions separated by insulating material regions  
A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor...
6551941 Method of forming a notched silicon-containing gate structure  
A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate...
6537921 Vertical metal oxide silicon field effect semiconductor diodes  
The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high...
6534384 Method for manufacturing SOI wafer including heat treatment in an oxidizing atmosphere  
A method for manufacturing an SOI wafer. The method includes forming an oxide film on a surface of at least one silicon wafer of two silicon wafers. The method also includes bonding the silicon...
6530380 Method for selective oxide etching in pre-metal deposition  
A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as...
6531349 Method of etching polycrystalline silicon film by using two consecutive dry-etching processes  
A method for fabricating a semiconductor device including the steps of: sequentially forming an oxide film and a polycrystalline silicon film overlying a substrate; and selectively dry-etching the...
6531067 Method for forming contact hole  
The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level...
6527968 Two-stage self-cleaning silicon etch process  
A process for etching a substrate 25 in an etching chamber 105, and simultaneously removing etch residue deposited on the surfaces of the walls 110 and components of the etching chamber 105. In one...
6518192 Two etchant etch method  
A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as...
6513537 Substrate processing method and substrate processing apparatus  
The present invention relates to a method of removing a polymer veil and a metal contamination deposited on a substrate having a metal layer. First, the polymer veils are removed by a chemical...
6506680 Method of forming connections with low dielectric insulating layers  
In a semiconductor manufacturing method, etching control is provided by introducing a material containing a material having at least one of an —H, —C, —CH, —CH2, and —CH3 radical component...
6500745 Method for manufacturing sidewall spacers of a semiconductor device with high etch selectivity and minimized shaving  
A method for manufacturing a field effect transistor includes a first step for etching 70%˜90% of the thickness of an insulating film (SiO2 or Si3N4) formed covering a gate electrode formed on a ...
6500767 Method of etching semiconductor metallic layer  
A method of etching a metallic layer having an anti-reflection layer thereon. The method includes performing a first etching operation using a fixed set of processing parameters to etch the...
6492280 Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls  
A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density...
6489248 Method and apparatus for etch passivating and etching a substrate  
A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and...
6482728 Method for fabricating floating gate  
A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed...
6479396 Dry polymer and oxide veil removal for post etch cleaning  
In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical based processes that do not remove...
6479398 Method of manufacturing an amorphous-silicon thin film transistor  
A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and...
6475922 Hard mask process to control etch profiles in a gate stack  
A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack, minimizing the formation of micro-trenches while achieving nearly...
6472306 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer  
A method of forming a dual damascene opening, comprising the following steps. A semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over...
6468920 Method for manufacturing contact hole in semiconductor device  
A method for manufacturing a contact hole in a semiconductor device which includes the steps of preparing an active matrix provided with a substrate and word lines formed on the substrate, forming...
6464892 Methods of fabricating microelectromechanical and microfluidic devices  
Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The...
6458494 Etching method  
Etching method applicable to a semiconductor device fabrication and an MEMS(Micro-Electro-Mechanical System) process, including the steps of forming an etching mask on a substrate, forming a...
6458657 Method of fabricating gate  
A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different...