|
Match
|
Document |
Document Title |
|
|
6821903 |
Method for making an integrated optical circuit
In order to manufacture an integrated optical circuit, a first mask is formed on a first region of a substrate and defines the shape of at least one optical device (such as a waveguide). A second...
|
|
|
6821901 |
Method of through-etching substrate
A method of through-etching a substrate that is simplified and by which the flow of ions can be kept to be regular during a plasma dry etching process, is provided. According to this method, a...
|
|
|
6821900 |
Method for dry etching deep trenches in a substrate
A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a...
|
|
|
6818562 |
Method and apparatus for tuning an RF matching network in a plasma enhanced semiconductor wafer processing system
A method and apparatus for operating a matching network within a plasma enhanced semiconductor wafer processing system that uses pulsed power to facilitate plasma processing.
|
|
|
6818557 |
Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance
The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed...
|
|
|
6818561 |
Control methodology using optical emission spectroscopy derived data, system for performing same
The present invention is generally directed to various control methodologies using optical emission spectroscopy derived data, and a system for performing same. In one illustrative embodiment, the...
|
|
|
6818563 |
Process and apparatus for removal of photoresist from semiconductor wafers using spray nozzles
A process for removing photoresist from semiconductor wafers is disclosed wherein at least one semiconductor wafer having at least one layer of photoresist is positioned in a process tank; ozone...
|
|
|
6815361 |
Method of fabricating anti-stiction micromachined structures
A method of fabricating micro-electromechanical system (MEMS) structures that can prevent stiction between a microstructure and a substrate or adjacent structures after etching for releasing the...
|
|
|
6815362 |
End point determination of process residues in wafer-less auto clean process using optical emission spectroscopy
A method for determining an endpoint of an in-situ cleaning process of a semiconductor processing chamber is provided. The method initiates with providing an optical emission spectrometer (OES)...
|
|
|
6815365 |
Plasma etching apparatus and plasma etching method
A plasma etching method for etching a sample within an etching chamber having a sidewall, an exchangeable jacket which is held inside of the sidewall, and a heating mechanism proximate to top end...
|
|
|
6815364 |
Tungsten hard mask
Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of said wafer, etching through said...
|
|
|
6815340 |
Method of forming an electroless nucleation layer on a via bottom
A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive...
|
|
|
6815359 |
Process for improving the etch stability of ultra-thin photoresist
An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the...
|
|
|
6815363 |
Method for nanomachining high aspect ratio structures
A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material...
|
|
|
6812152 |
Method to obtain contamination free laser mirrors and passivation of these
A method to obtain contamination free surfaces of a material chosen from the group comprising GaAs, GaAlAs, InGaAs, InGaAsP and InGaAs at crystal mirror facets for GaAs based laser cavities. The...
|
|
|
6812151 |
Method of etching
An etching method is carried out by an etching system comprising a gas supply port for supplying an etching gas, a plasma producing vessel defining a plasma producing chamber in which the etching...
|
|
|
6812044 |
Advanced control for plasma process
A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either...
|
|
|
6809036 |
Dry silylation plasma etch process
A dry silylation process involving plasma etching of a substrate ( 100 ) having an upper surface ( 100 S) coated with a first layer (L 1 ) of silylatable material with one or more silylated regions...
|
|
|
6806200 |
Method of improving etch uniformity in deep silicon etching
A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including...
|
|
|
6803319 |
Process for optically erasing charge buildup during fabrication of an integrated circuit
A process for optically reducing charge build-up in an integrated circuit includes exposing the integrated circuit or portions thereof to a broadband radiation source. The process effectively...
|
|
|
6803309 |
Method for depositing an adhesion/barrier layer to improve adhesion and contact resistance
A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor...
|
|
|
6803320 |
Protective tape applying and separating methods
A protective tape is applied by a tape applying mechanism on a surface of a wafer suction-supported by a chuck table. The protective tape is cut to the shape of the wafer by a cutter unit. This...
|
|
|
6800213 |
Precision dielectric etch using hexafluorobutadiene
An oxide etching recipe including a heavy hydrogen-free fluorocarbon having F/C ratios less than 2, preferably C 4 F 6 , an oxygen-containing gas such as O 2 or CO, a lighter fluorocarbon or...
|
|
|
6800559 |
Method and apparatus for generating H20 to be used in a wet oxidation process to form SiO2 on a silicon surface
Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species...
|
|
|
6797635 |
Fabrication method for lines of semiconductor device
A fabrication method for lines of a semiconductor device provides a substrate with a deposition layer already formed thereon, followed by forming a photoresist layer on the deposition layer....
|
|
|
6797639 |
Dielectric etch chamber with expanded process window
A capacitively coupled reactor for plasma etch processing of substrates at subatmospheric pressures includes a chamber body defining a processing volume, a lid provided upon the chamber body, the...
|
|
|
6797638 |
Plasma-etching process for molybdenum silicon nitride layers on half-tone phase masks based on gas mixtures containing monofluoromethane and oxygen
A method for etching phase shift layers of half-tone phase masks includes etching a phase shift layer by using a plasma which is obtained from CH 3 F and O 2 . A high cathode power is used for the...
|
|
|
6797636 |
Process of fabricating DRAM cells with collar isolation layers
A process of preparing DRAM cells with collar isolation layers that isolate the trench top with vertical cell and active area from the buried plate to eliminate the space normally required by a...
|
|
|
6797633 |
In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning
After via etch, a low-k dielectric layer ( 104 ) is treated with an in-situ O 2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films ( 104 ), such as...
|
|
|
6794295 |
Method to improve stability and reliability of CVD low K dielectric
A process for depositing, through plasma enhanced chemical vapor deposition, inorganic films having low dielectric constant is disclosed. After deposition under low power for a few seconds the...
|
|
|
6794294 |
Etch process that resists notching at electrode bottom
A semiconductor device is manufactured using a small amount of nitrogen in the gate electrode etch process to minimize notching at the bottom of the electrode. Consistent with one embodiment of the...
|
|
|
6794300 |
Mechanically scanned wet chemical processing
A substrate such as a semiconductor wafer is move across the top of an open trough while a liquid is maintained in the trough at a level just above the walls of the trough, as by supplying the...
|
|
|
6794297 |
Method for etching an antireflective coating and for fabricating a semiconductor device
To determine an optimum addition ratio of ethyl alcohol in the etching gas in a plasma etching unit, an ethyl alcohol addition ratio at which the isotropic etching rate of the etching mask is...
|
|
|
6794301 |
Pulsed plasma processing of semiconductor substrates
Apparatus and methods for an improved plasma processing. A first power source alternates between high and low power cycles to produce and sustain a plasma, and a second power source alternates...
|
|
|
6794298 |
CF4&plus H2O plasma ashing for reduction of contact/via resistance
The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by...
|
|
|
6794299 |
Various methods of controlling conformal film deposition processes, and a system for accomplishing same
Various methods of controlling conformal film deposition processes, and a system for accomplishing same are disclosed. In one embodiment, the method comprises forming a plurality of features above...
|
|
|
6790782 |
Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack...
|
|
|
6790766 |
Method of fabricating semiconductor device having low dielectric constant insulator film
A method of fabricating a semiconductor device capable of increasing the selectivity of a low dielectric constant insulator film to an etching mask layer such as an etching stopper film without...
|
|
|
6790777 |
Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device
The present invention relates to a method for improving an interface of a semiconductor device. The method comprises providing a first and second substrate having an oxidized region, and...
|
|
|
6787877 |
Method for filling structural gaps and integrated circuitry
A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed...
|
|
|
6787474 |
Manufacture method for semiconductor device having silicon-containing insulating film
The surface of an insulating film made of silicon-containing insulating material is covered with a mask pattern. The insulating film is dry-etched by using the mask pattern as a mask and etching...
|
|
|
6787475 |
Flash step preparatory to dielectric etch
A dielectric plasma etch method particularly useful for assuring that residue does not form in large open pad areas used for monitoring etching of narrow via and contact holes. The main dielectric...
|
|
|
6787054 |
Two-stage etching process
A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the...
|
|
|
6784109 |
Method for fabricating semiconductor devices including wiring forming with a porous low-k film and copper
Semiconductor devices having a wiring construction consisting of a conductive layer (a copper layer) and an insulating layer (a porous insulator layer with low dielectric constant) are fabricated....
|
|
|
6784111 |
Etching methods and apparatus and substrate assemblies produced therewith
Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define...
|
|
|
6784108 |
Gas pulsing for etch profile control
Etch profile control with pulsed gas flow and its applications to etching such as anisotropic etching of high aspect ratio features and etching of self-aligned contact structures in various...
|
|
|
6783626 |
Treatment and evaluation of a substrate processing chamber
A substrate processing apparatus has a chamber having a substrate transport to transport a substrate onto a substrate support in the chamber, a gas supply to provide a gas in the chamber, a gas...
|
|
|
6780776 |
Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer
A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited...
|
|
|
6780777 |
Method for forming metal layer of semiconductor device
The disclosure pertains to a method for forming a metal layer of a semiconductor device including the steps of: removing a residual native oxide from a contact hole forming a metal junction layer...
|
|
|
6780753 |
Airgap for semiconductor devices
Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately...
|