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8183152 Method of fabricating semiconductor device  
A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is...
8173548 Reverse planarization method  
A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer...
8143137 Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate  
The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device...
8097811 Substrate for suspension  
A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the...
8039389 Semiconductor device having an organic anti-reflective coating (ARC) and method therefor  
In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a...
8030217 Simplified pitch doubling process flow  
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over...
8017464 Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device  
As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide...
8008205 Methods for producing a semiconductor device having planarization films  
A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a...
7998868 Self-aligned masks using multi-temperature phase-change materials  
A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer,...
7985684 Actuating transistor including reduced channel length  
A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned...
7968468 Substrate treatment apparatus and substrate treatment method  
In a substrate treatment method for supplying a coating solution to a substrate with projections and depressions on a front surface thereof to form a coating film on the front surface of the...
7947569 Method for producing a semiconductor including a foreign material layer  
A method for producing a semiconductor including a material layer. In one embodiment a trench is produced having two opposite sidewalls and a bottom, in a semiconductor body. A foreign material...
7915064 Processing for overcoming extreme topography  
A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of...
7911001 Methods for forming self-aligned dual stress liners for CMOS semiconductor devices  
CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner...
7902074 Simplified pitch doubling process flow  
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises...
7879645 Fill-in etching free pore device  
A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the...
7879643 Memory cell with memory element contacting an inverted T-shaped bottom electrode  
Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the...
7867902 Methods of forming a contact structure  
In a method of forming a contact structure, a first insulation layer including a first contact hole is formed on a substrate. A metal layer including tungsten is formed to fill the first contact...
7863196 Self-aligned dielectric cap  
A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A...
7855148 Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features  
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are...
7846756 Nanoimprint enhanced resist spacer patterning method  
A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features...
7833872 Uniform recess of a material in a trench independent of incoming topography  
Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major...
7799690 Method for fabricating semiconductor integrated circuit device  
A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and...
7772122 Sidewall forming processes  
An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on...
7759261 Method for producing layers located on a hybrid circuit  
A method for obtaining layers defined on a hybrid circuit. The hybrid circuit including a substrate and at least one elementary circuit that includes a first facet and a second facet, being...
7745343 Method for fabricating semiconductor device with fuse element  
A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer...
7709390 Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features  
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are...
7679149 Method of removing refractory metal layers and of siliciding contact areas  
A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for...
7678651 Method for fabricating semiconductor device  
A method for fabricating a semiconductor device includes: providing a substrate structure in which a plurality of gate lines are already formed; forming a capping layer over the substrate...
7670925 Semiconductor device, method of manufacturing same, and apparatus for designing same  
A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic...
7615480 Methods of post-contact back end of the line through-hole via integration  
Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In...
7507669 Gap tuning for surface micromachined structures in an epitaxial reactor  
A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one...
7462504 Surface-emitting type light-emitting diode and fabrication method thereof  
A surface-emitting type light-emitting diode includes a substrate, a p-n junction layer elevated on a portion of the substrate to emit light, and a first isolator layer formed on a sidewall of the...
7435683 Apparatus and method for selectively recessing spacers on multi-gate devices  
Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described...
7432120 Method for realizing a hosting structure of nanometric elements  
Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side...
7410863 Methods of forming and using memory cell structures  
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a...
7390743 Methods for forming a structured tungsten layer and forming a semiconductor device using the same  
A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A...
7384799 Method to avoid amorphous-si damage during wet stripping processes in the manufacture of MEMS devices  
A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous...
7375012 Method of forming multilayer film  
This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.
7300886 Interlayer dielectric for charge loss improvement  
A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes...
7268075 Method to reduce the copper line roughness for increased electrical conductivity of narrow interconnects (<100nm)  
Embodiments of the present invention provide methods to reduce the copper line roughness for increased electrical conductivity in narrow interconnects having a width of less than 100 nm. These...
7247569 Ultra-thin Si MOSFET device structure and method of manufacture  
The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate...
7179757 Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials  
Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious...
7180706 Magnetic heads and semiconductor devices and surface planarization processes for the fabrication thereof  
A magnetic head according to one embodiment includes a pole piece made of a magnetic material; one or more magnetic pedestals formed over the pole piece; an insulator material formed over the pole...
7112458 Method of forming a liquid crystal display  
An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom...
7084059 CMP system for metal deposition  
A system for dished metal redevelopment by providing a metal deposition solution at an interface between a moving semiconductor wafer and a moving polishing pad, which deposits metal onto dished...
7078312 Method for controlling etch process repeatability  
Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries...
7033930 Interconnect structures in a semiconductor device and processes of formation  
Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate,...
7022579 Method for filling via with metal  
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a...
7009811 Surface planarization processes for the fabrication of magnetic heads and semiconductor devices  
Surface planarization processes for the fabrication of magnetic heads and semiconductor devices are described herein. In one illustrative example, magnetic structures are formed over a substrate...
Matches 1 - 50 out of 383 1 2 3 4 5 6 7 8 >