Matches 1 - 50 out of 104 1 2 3 >
Match Document Document Title
7575995 Method of forming fine metal pattern and method of forming metal line using the same  
There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first...
7507618 Method for making electronic devices using metal oxide nanoparticles  
A method of making a thin film transistor comprises (a) solution depositing a dispersion comprising semiconducting metal oxide nanoparticles onto a substrate, (b) sintering the nanoparticles to...
7479455 Method for manufacturing semiconductor wafer  
A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may...
7410863 Methods of forming and using memory cell structures  
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a...
7357873 Polymide thin film self-assembly process  
The invention presents a novel polyimide-based thin film self-assembly technology, including five process steps described as follows: (1) deposits a sacrificial layer and a low-stress...
7348278 Method of making nitride-based compound semiconductor crystal and substrate  
A method of making a nitride-based compound semiconductor crystal has the step of growing a nitride-based compound semiconductor crystal with a predetermined thickness by using a nitride-based...
7335255 Manufacturing method of semiconductor device  
The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of...
7264976 Advance ridge structure for microlens gapless approach  
A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of...
7226865 Process for forming pattern and method for producing liquid crystal display apparatus  
A process for forming a pattern contains steps of: forming a first mask pattern on a film to be etched on a substrate; forming a first pattern of the film to be etched by using the first mask...
7192867 Protection of low-k dielectric in a passivation level  
In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered...
7176087 Methods of forming electrical connections  
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in...
7144817 Etching solutions and processes for manufacturing flexible wiring boards  
The disclosure relates to methods and solutions for precisely and rapidly etching a polyimide resin layer. Etching solutions of the present invention include 3–65% by weight of a diol containing...
7060623 Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern  
A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper...
7053407 Liquid crystal display device and method for manufacturing the same  
Disclosed are a liquid crystal display device and a method for manufacturing the same, in which wirings connected between pads and an integrated circuit is protected from being corroded. A pixel...
7022608 Method and composition for the removal of residual materials during substrate planarization  
A method, composition, and computer readable medium for planarizing a substrate. In one aspect, the composition includes one or more chelating agents and ions of at least one transition metal, one...
7022579 Method for filling via with metal  
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a...
6979526 Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs  
A method of manufacturing a resistive semiconductor memory device ( 10 ), comprising depositing an insulating layer ( 34 ) over a workpiece ( 30 ), and defining a pattern for a plurality of...
6972259 Method for forming openings in low dielectric constant material layer  
The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer...
6916743 Semiconductor device and method for manufacturing thereof  
A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above...
6914000 Polishing method, polishing system and process-managing system  
A polishing method of the present invention is a polishing method for planarizing a film to be polished that is deposited on a wafer, and includes a step (a) of establishing a polishing rate...
6803308 Method of forming a dual damascene pattern in a semiconductor device  
The present invention is directed to a method of forming a dual damascene pattern in a fabrication process of a semiconductor device, which is capable of simplifying a fabrication process of a...
6774042 Planarization method for deep sub micron shallow trench isolation process  
A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches...
6753259 Method of improving the bondability between Au wires and Cu bonding pads  
Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips...
6746888 Display and fabricating method thereof  
A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the...
6743724 Planarization process for semiconductor substrates  
A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are...
6682820 Recession resistant coated ceramic part  
A recession resistant coated ceramic part. The ceramic part has a ceramic substrate and a recession resistant coating disposed on the substrate. The coating includes a plurality of layers diffusion...
6645865 Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes  
Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect...
6639285 Method for fabricating a semiconductor device  
A method for making a semiconductor device is provided. The method allows for depositing a layer of a doped dielectric. The method further allows for executing plasma etching so that one or more...
6627551 Method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process  
This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel...
6620534 Film having enhanced reflow characteristics at low thermal budget  
A method of forming a film having enhanced reflow characteristics at low thermal budget is disclosed, in which a surface layer of material is formed above a base layer of material, the surface...
6617252 Monolithic low dielectric constant platform for passive components and method  
A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon...
6602793 Pre-clean chamber  
An improved pre-clean chamber of a semiconductor processing system minimizes the generation of particulates during processing, thereby decreasing contamination levels that can adversely affect...
6555461 Method of forming low resistance barrier on low k interconnect  
A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is...
6479389 Method of doping copper metallization  
This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed...
6451181 Method of forming a semiconductor device barrier layer  
A method for forming an improved copper inlaid interconnect (FIG. 11 ) begins by performing an RF preclean operation ( 408 ) on the inlaid structure in a chamber ( 10 ). The RF preclean rounds...
6413870 Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby  
A method for removing scratches from a dielectric layer comprising the steps of: providing a layer of a reflowable dielectric material; and heating the dielectric layer to a temperature sufficient...
6368957 Semiconductor device and method for manufacturing semiconductor device  
In the method for manufacturing a semiconductor device according to the present invention, after forming a BPSG film 110 on a silicon substrate 100 , a preparatory hole 120 that reaches a...
6342448 Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process  
A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed...
6277754 Method of planarizing dielectric layer  
A method of planarizing a dielectric layer comprising the steps of providing a substrate having structures already formed thereon, and then forming a borophosphosilicate glass layer over the...
6277748 Method for manufacturing a planar reflective light valve backplane  
A method for manufacturing a planar reflective light valve backplane includes the steps of providing a substrate (e.g., a reflective backplane) including a plurality of surface projections (e.g.,...
6245688 Dry Air/N2 post treatment to avoid the formation of B/P precipitation after BPSG film deposition  
A method to store wafers, immediately after the deposition of a layer of BPSG, into an environment of dry air or dry N 2 or dry Ar or a N 2 O plasma chamber. This storage can occur over a...
6225227 Method for manufacturing semiconductor device  
In a method for manufacturing a semiconductor device in a wafer having a device formation area and an inspection pattern formation area, an interconnection layer is formed in the device formation...
6184137 Structure and method for improving low temperature copper reflow in semiconductor features  
We have discovered that complete copper filling of semiconductor features such as trenches and vias, without the formation of trapped voids, can be accomplished using a copper reflow process when...
6180510 Method of manufacturing a substantially flat surface of a semiconductor device through a polishing operation  
For giving a device surface to a semiconductor device comprising a semiconductor substrate portion which has a substrate surface and a protruding portion protruding from the substrate surface, a...
6177337 Method of reducing metal voids in semiconductor device interconnection  
The occurrence of defects in interconnect metal structure is reduced or eliminated by a method wherein a semiconductor substrate having a dielectric layer, a metal-containing electrically...
6153478 STI process for eliminating kink effect  
The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the...
6140242 Method of forming an isolation trench in a semiconductor device including annealing at an increased temperature  
A method of forming an isolation trench in a semiconductor device results in increasing trench isolation characteristics by optimizing an annealing temperature thereby removing substrate defects...
6127271 Process for dry etching and vacuum treatment reactor  
A process for dry etching a surface within a vacuum treatment reactor includes evacuating the reactor, generating a glow discharge within said reactor, feeding a reactive etching gas into said...
6114219 Method of manufacturing an isolation region in a semiconductor device using a flowable oxide-generating material  
A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion...
6103624 Method of improving Cu damascene interconnect reliability by laser anneal before barrier polish  
Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the...
Matches 1 - 50 out of 104 1 2 3 >