Matches 351 - 400 out of 899 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
6667237 Method and apparatus for patterning fine dimensions  
A process of forming fine repetitive geometries using a mask having large mask dimensions. The pitch of the masking pattern on the mask is divided by the process to obtain a smaller pitch in the...
6667240 Method and apparatus for forming deposited film  
A method for forming a deposited film, comprising generating plasma in a plurality of successive vacuum containers and continuously forming a deposited film on a belt-like substrate while...
6664197 Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components  
A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process...
6664189 Removal of wafer edge defocus due to CMP  
At the conclusion of chemical mechanical polishing (CMP) there is found to be a topography difference at the periphery of the wafer. For example, for a 200 mm wafer, the oxide surface in a...
6660651 Adjustable wafer stage, and a method and system for performing process operations using same  
A process tool comprised of an adjustable wafer stage and various methods and systems for performing process operations using same is disclosed herein. In one illustrative embodiment, the process...
6660570 Method of fabricating a high voltage semiconductor device using SIPOS  
A high voltage semiconductor device including a semiconductor substrate on which a semi-insulating polycrystalline silicon layer is formed to alleviate electric field concentration in a field...
6656843 Single mask trench fred with enlarged Schottky area  
A single mask process is described for making a trench type fast recovery process. The single mask defines slots in a photoresist for locally removing strips of nitride and oxide from atop silicon...
6653058 Methods for reducing profile variation in photoresist trimming  
A method of removing photoresist material from a semiconductor substrate includes providing a semiconductor substrate having a patterned photoresist mask. A layer comprised of polymer material is...
6645865 Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes  
Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect...
6642148 RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist  
The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral...
6638870 Forming a structure on a wafer  
A method for fabricating a structure on an integrated circuit (IC) wafer, includes providing a material onto a surface of the wafer and shaping the material to have a shape corresponding to the...
6633427 Method of forming photonic crystals using a semiconductor-based fabrication process  
A photonic crystal is formed on a semiconductor substrate using a semiconductor-based fabrication process by forming a number of alternating layers of material that have different dielectric...
6630404 Reducing feature dimension using self-assembled monolayer  
A method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist over the layer of material; exposing the layer of photoresist to a source...
6627552 Method for preparing epitaxial-substrate and method for manufacturing semiconductor device employing the same  
The present invention provides a method for preparing epitaxial-substrate, for growing a multilayered structure of GaN based semiconductor layers on the epitaxial-substrate so as to construct a...
6627551 Method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process  
This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel...
6624079 Method for forming high resistance resistor with integrated high voltage device process  
The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion...
6622907 Sacrificial seed layer process for forming C4 solder bumps  
Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive...
6620733 Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics  
A method for etching features in an integrated circuit wafer, the wafer incorporating at least one dielectric layer is provided. Generally, the wafer is disposed within a reaction chamber. An...
6620575 Construction of built-up structures on the surface of patterned masking used for polysilicon etch  
The present invention pertains to a method for depositing built-up structures on the surface of patterned masking material used for semiconductor device fabrication. Such built-up structures are...
6613677 Long range ordered semiconductor interface phase and oxides  
A semiconductor processing method capable of producing highly ordered, ultra thin dielectrics, including gate oxide and other semiconductor dielectrics, and interphase phases with low defect...
6610602 Magnetic field sensor and method of manufacturing same using a self-organizing polymer mask  
A giant magnetoresistance (GMR) sensor is formed using a self organizing diblock copolymer as an etching mask. The diblock copolymer is deposited over a magnetic layer and is self organized into...
6610603 Method of manufacturing a capacitor  
In order to prevent a capacitance element from suffering fluctuation in the capacitance value and deterioration of the reliability caused in the step for planarizing the surface of the substrate...
6610597 Method of fabricating a semiconductor device  
A semiconductor manufacturing process is disclosed that may form a contact structure with a tungsten plug. A contact structure hole may be adequately filled with tungsten, while avoiding plug loss,...
6610604 Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask  
A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si 3 N 4 or an SiO 2 /Si 3 N 4 stack gate dielectric layer. A gate material layer is...
6605546 Dual bake for BARC fill without voids  
A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating...
6605537 Polishing of metal substrates  
A method of polishing a semiconductor substrate by adjusting the polishing composition with a BTA concentration that raises the metal removal rate when polishing at a relatively high polishing...
6605540 Process for forming a dual damascene structure  
The invention describes a method for forming a dual damascene structure. An etch stop layer ( 150 ) is formed on a dielectric layer ( 140 ). A second dielectric layer ( 160 ) is formed on the etch...
6602794 Silylation process for forming contacts  
A method of forming narrow trenches in a layer of photoresist is disclosed. The method includes providing a photoresist layer and patterning the photoresist layer to form a plurality of apertures...
6593177 Self aligned method of forming a semiconductor memory array of floating gate memory cells, and a memory array made thereby  
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate...
6593239 Chemical mechanical polishing method useful for copper substrates  
A chemical mechanical polishing slurry comprising a film forming agent, an oxidizer, a complexing agent and an abrasive, and a method for using the chemical mechanical polishing slurry to remove...
6589873 Process for manufacturing a semiconductor device  
There is disclosed a process for manufacturing a semiconductor device. When a metal film is formed by plasma CVD in a contact hole which penetrates an interlayer insulating film and reaches an...
6589874 Method for forming electromigration-resistant structures by doping  
A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the...
6582512 Method of forming three-dimensional photonic band structures in solid materials  
A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of...
6579808 Method of fabricating a semiconductor device  
A method for fabricating a semiconductor device capable of maintaining contact hole of fine size when the contact hole for bit line formation is defined. The method comprises the steps of:...
6579798 Processes for chemical-mechanical polishing of a semiconductor wafer  
A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and...
6576563 Method of manufacturing a semiconductor device employing a fluorine-based etch substantially free of hydrogen  
The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate,...
6576555 Method of making upper conductive line in dual damascene having lower copper lines  
A method of making upper conductive lines in dual damascene process having lower copper conductive lines is disclosed. The processes begin from a substrate having lower copper conductive lines and...
6569765 Hybrid deposition system and methods  
A hybrid deposition system includes a reactor chamber, at least one heating unit, a first reagent gas source, a metallo-organic source, a second reagent gas source, and a valve unit for stopping...
6569777 Plasma etching method to form dual damascene with improved via profile  
A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer comprising a first feature opening anisotropically etched though a...
6569768 Surface treatment and capping layer process for producing a copper interface in a semiconductor device  
A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma...
6566264 Method for forming an opening in a semiconductor device substrate  
In one embodiment, a first dielectric film ( 24 ), and a second dielectric film ( 32 ) are formed over a substrate ( 10 ). The substrate is cured to at least partially change a property of the...
6555477 Method for preventing Cu CMP corrosion  
A method for preventing or reducing corrosion of copper containing semiconductor features during chemical mechanical polishing (CMP) including providing a semiconductor wafer polishing surface...
6551937 Process for device using partial SOI  
A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth...
6551936 Method of etching patterns into epitaxial material  
An improved method for etching a pattern in a semiconductor material is based on the formation of an InP grating mask on the semiconductor material. The formation of the InP grating mask involves...
6551905 Wafer adhesive for semiconductor dry etch applications  
A method is provided for backside processing a semiconductor wafer ( 10 ) including applying a polymer based protective coating ( 16 ) on the wafer, depositing a barrier layer of ceramic ( 18 ) on...
6548406 Method for forming integrated circuit having MONOS device and mixed-signal circuit  
A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory...
6548410 Method of fabricating wires for semiconductor devices  
A method of forming wires for semiconductor devices can restrict increase of a wires resistance and a contact resistance of the semiconductor device by forming a plug without generating a void or...
6544905 Metal gate trim process by using self assembled monolayers  
In a method of forming a metal gate of a semiconductor device, a substrate is provided, which includes a substrate body covered by a dielectric layer. A metal body having top and side surface is...
6538273 Ferroelectric transistor and method for fabricating it  
A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the...
6537917 Method for fabricating electrically insulating layers  
This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching...
Matches 351 - 400 out of 899 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >