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7129167 |
Methods and systems for a stress-free cleaning a surface of a substrate
A method of cleaning a substrate includes receiving a substrate and applying a stress-free cleaning process to the top surface of the substrate. The substrate includes a top surface that is...
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7129175 |
Method of manufacturing semiconductor device
A semiconductor device manufacturing method comprises forming a first insulating film including silicon, carbon, nitrogen, and hydrogen above a substrate in a first chamber, carrying the substrate...
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7129109 |
Method for structuring an oxide layer applied to a substrate material
The invention relates to a method for structuring an oxide layer applied to a substrate material. The aim of he invention is to provide an inexpensive method for structuring such an oxide layer. To...
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7125778 |
Method for fabricating a self-aligning mask
A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are...
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7122455 |
Patterning with rigid organic under-layer
For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask...
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7122473 |
Edge and bevel cleaning process and system
The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically...
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7112243 |
Method for producing Group III nitride compound semiconductor
The present invention provides a method for producing a Group III nitride compound semiconductor, which method permits only minimal reaction of the semiconductor with a hetero-substrate during...
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7112822 |
Semiconductor device using partial SOI substrate and manufacturing method thereof
A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer...
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7112458 |
Method of forming a liquid crystal display
An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom...
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7109095 |
Method for fabricating semiconductor device
Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the...
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7105395 |
Programming and erasing structure for an NVM cell
A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is...
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7105452 |
Method of planarizing a semiconductor substrate with an etching chemistry
The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the...
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7105448 |
Method for peeling off semiconductor element and method for manufacturing semiconductor device
A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor...
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7101770 |
Capacitive techniques to reduce noise in high speed interconnections
Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an...
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7098135 |
Semiconductor device including bit line formed using damascene technique and method of fabricating the same
A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove...
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7097779 |
Processing system and method for chemically treating a TERA layer
A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment,...
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7084065 |
Method for fabricating a semiconductor device
A method for fabricating a semiconductor device that prevents the formation of a side etch caused by fluoride (CF x ) produced when a barrier insulating film is etched. As shown in FIG. 1 (G), an...
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7081403 |
Thin leadless plastic chip carrier
A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe...
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7078345 |
Method for manufacturing a semiconductor device
There is disclosed a method of manufacturing a semiconductor device comprising forming a diffusion region containing arsenic impurity at a concentration of 1×10 20 cm −3 or more in an element...
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7067424 |
Method of manufacturing an electronic device
The present invention provides for a method of providing copper metallization on a semiconductor body, including the step of depositing copper in a nitrogen-containing atmosphere so as to form a...
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7067329 |
Methods of forming ferroelectric memory devices
A ferroelectric memory device and a method of fabricating the same are provided. The device includes a substrate where a conductive region is formed and an interlayer insulating layer. The...
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7067429 |
Processing method of forming MRAM circuitry
A method of forming integrated circuitry includes chemical vapor depositing a silicon carbide comprising layer over a substrate at a temperature of no greater than 500° C. Plasma etching is...
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7064059 |
Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer
There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer...
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7052997 |
Method to form etch and/or CMP stop layers
In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is non-conformal in that the oxide is thicker over...
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7053004 |
Decreasing the residue of a silicon dioxide layer after trench etching
A semiconductor device is formed using a BARC (bottom antireflective coating) that minimizes the formation of fences around the via holes. The BARC is formed from an organic antireflective layer...
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7052552 |
Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD
A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma...
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7053005 |
Method of forming a silicon oxide layer in a semiconductor manufacturing process
A method of forming a silicon oxide layer in a semiconductor manufacturing process includes forming a planar spin on glass (SOG) layer by coating an SOG composition onto a semiconductor substrate...
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7049241 |
Method for forming a trench in a layer or a layer stack on a semiconductor wafer
Preferably using a positive resist, a resist ridge ( 20 ) is formed in a photosensitive resist ( 16 ) applied on a semiconductor wafer ( 1 ) above a hard mask layer ( 12 ). The resist ridge ( 20 )...
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7045450 |
Method of manufacturing semiconductor device
Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming gates on a substrate, forming junction areas on a surface of the substrate, forming a first...
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7041227 |
Method for revealing crystalline defects and/or stress field defects at the molecular adhesion interface of two solid materials
A process for permitting defects or stresses in a structure to be revealed, including (a) securing by molecular bonding of a face of a first element containing crystalline material with a face of a...
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7042751 |
Method to produce data cell region and system region for semiconductor memory
The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus...
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7033941 |
Method of producing semiconductor devices using chemical mechanical polishing
The present invention is related to a method for producing semiconductor devices from a semiconductor substrate, comprising providing a substrate having on its surface a number of elevated areas...
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7030021 |
Method of fabricating metal interconnection of semiconductor device
A method of fabricating a metal interconnection of semiconductor device is disclosed. A metal interconnection fabricating method according to the present invention comprises the steps of depositing...
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7030045 |
Method of fabricating oxides with low defect densities
A method and system for forming a low defect oxide in a plasma processing chamber. By pulsing at least one of an RF power source and a processing gas, the growth of the oxide can be regulated....
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7030020 |
Method to shrink cell size in a split gate flash
A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the...
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7022604 |
Method of forming spatial regions of a second material in a first material
A surface-transformation method of forming regions of a second material in a first solid material to control the properties of the first solid material is disclosed. The regions of the second...
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7022609 |
Manufacturing method of a semiconductor substrate provided with a through hole electrode
A manufacturing method of a semiconductor substrate provided with a through hole electrode is proposed. In accordance with the methods, it is possible to effectively form a through hole electrode...
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7018575 |
Method for assembly of complementary-shaped receptacle site and device microstructures
A method for assembly including the steps of: (a) providing a plurality of microstructure components with each of the components having a bottom with the same three dimensional shape; (b) forming...
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7018780 |
Methods for controlling and reducing profile variation in photoresist trimming
A method for controlling a removal of photoresist material from a semiconductor substrate is provided. The method includes providing the semiconductor substrate having a photoresist mask formed...
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7015144 |
Compositions including perhydro-polysilazane used in a semiconductor manufacturing process and methods of manufacturing semiconductor devices using the same
Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity...
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7015147 |
Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer
A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si 1−x Ge x layer, includes preparing a silicon substrate; growing an epitaxial Si 1−x Ge x layer on the...
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7008874 |
Process for reclaiming semiconductor wafers and reclaimed wafers
The present invention is directed to a process for reclaiming for reuse a single crystal silicon wafer removed from an aborted semiconductor device fabrication process. The process includes (a)...
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7005385 |
Method for removing a resist mask with high selectivity to a carbon hard mask used for semiconductor structuring
The present invention relates to a method for removing a resist selective to a carbon hard mask including providing an etching plasma comprising of at least hydrogen at a predetermined temperature...
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7001854 |
Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures
Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.13 micron) gaps with significantly...
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7001849 |
Surface treatment and protection method for cadmium zinc telluride crystals
A method for treatment of the surface of a CdZnTe (CZT) crystal that provides a native dielectric coating to reduce surface leakage currents and thereby, improve the resolution of instruments...
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6995095 |
Methods of simultaneously fabricating isolation structures having varying dimensions
Shallow trench isolation structures are simultaneously fabricated such that ones in a cell region have first-type features and others in a periphery region have second-type features. The first-type...
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6992003 |
Integration of ultra low K dielectric in a semiconductor fabrication process
A backend semiconductor fabrication process includes forming an interlevel dielectric (ILD) overlying a wafer substrate by forming a low K dielectric (K<3.0) overlying the substrate of the...
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6992010 |
Gate structure and method of manufacture
A method of forming a gate structure. A gate oxide layer, a polysilicon layer, a metallic layer and an insulation layer are sequentially formed over a substrate. Using a definite height level to be...
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6984858 |
Semiconductor device and manufacturing method thereof
In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each...
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6979651 |
Method for forming alignment features and back-side contacts with fewer lithography and etch steps
The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a...
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