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6410443 |
Method for removing semiconductor ARC using ARC CMP buffing
The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the...
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6403485 |
Method to form a low parasitic capacitance pseudo-SOI CMOS device
A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating...
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6403486 |
Method for forming a shallow trench isolation
A method is disclosed to form a shallow trench isolation (STI) without reverse short channel effect. This is accomplished by forming oxidized polysilicon spacers in the dielectric layers above the...
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6391220 |
Methods for fabricating flexible circuit structures
Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release...
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6391749 |
Selective epitaxial growth method in semiconductor device
A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial...
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6383944 |
Micropatterning method
By forming a lift-off resist pattern on a surface of a first layer, forming a second layer over the first layer surface including the resist pattern, removing the resist pattern to partially expose...
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6380088 |
Method to form a recessed source drain on a trench side wall with a replacement gate technique
An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed...
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6380101 |
Method of forming patterned indium zinc oxide and indium tin oxide films via microcontact printing and uses thereof
Microcontact printing to pattern a self-assembled monolayer (SAM) of an alkanephosphonic acid on a film of indium zinc oxide (IZO). The SAM is robust enough to protect the undelying IZO from wet...
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6379989 |
Process for manufacture of microoptomechanical structures
A microoptomechanical structure produced by defining a microoptical structure in a single-crystal silicon layer separated by an insulator layer from a handle wafer, such as a SOI wafer, selectively...
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6380103 |
Rapid thermal etch and rapid thermal oxidation
At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step...
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6376885 |
Semiconductor structure with metal silicide and method for fabricated the structure
A method is directed to form a semiconductor device with silicide formed by a metal layer associated with a deposited silicon layer by providing a substrate. A field oxide layer is formed on a...
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6377866 |
Device for engraving and inspecting a semiconductor wafer identification mark
A device operable to apply an identification mark to a semiconductor wafer and inspect the applied mark immediately after its application. Engraving information and wafer thickness data are suppled...
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6372650 |
Method of cleaning substrate and method of manufacturing semiconductor device
A method of cleaning a substrate is provided which can remove contamination after treatment of a substrate surface by use of chemicals etc. prior to film formation. The method of cleaning the...
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6369396 |
Calibration target for electron beams
A scattering target for use in a particle beam system is formed from a grid of gold on a substrate of carbon, with an intermediate smoothing layer (e.g. copper) on the carbon to provide a surface...
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6365518 |
Method of processing a substrate in a processing chamber
Methods for processing a substrate are disclosed. In one embodiment of the invention, a substrate with a first layer and an oxide layer on the substrate is placed in a processing chamber. The oxide...
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6365521 |
Passivation for tight metal geometry
A method of passivating an integrated circuit comprising providing an integrated circuit having a top side including a bond pad, depositing a first dielectric over said top side of said integrated...
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6362104 |
Method for polishing a substrate using a CMP slurry
A chemical mechanical polishing composition comprising an oxidizing agent and at least one solid catalyst, the composition being useful when combined with an abrasive or with an abrasive pad to...
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6358840 |
Forming and filling a recess in interconnect with alloy to minimize electromigration
In a method for filling an interconnect opening to form an interconnect of an integrated circuit, the interconnect opening is formed within an insulating layer. The interconnect opening is...
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6355553 |
Method of forming a metal plug in a contact hole
A method of forming a metal plug, which method has the steps of depositing a metal film on an insulating film after formation of a contact opening in the insulating film and etching the metal film...
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6352930 |
Bilayer anti-reflective coating and etch hard mask
In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an...
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6350488 |
Mass synthesis method of high purity carbon nanotubes vertically aligned over large-size substrate using thermal chemical vapor deposition
A method of synthesizing high purity carbon nanotubes vertically aligned over a large size substrate by thermal chemical vapor deposition (CVD). In the synthesis method, isolated nano-sized...
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6350695 |
Pillar process for copper interconnect scheme
A method for forming reliable inter-level metal interconnections in semiconductor integrated circuits is described where pillars are formed to connect between different metal layers. A first...
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6348416 |
Carrier substrate for producing semiconductor device
In order to improve adhesion between a plated film which functions as an external connection terminal of a semiconductor device and a surface of a resin protuberance and to improve reliability, a...
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6346481 |
Method of reducing pitting of a coated heater
Provided herein is a method of depositing a film on a substrate in a high temperature chemical vapor deposition (CVD) reactor, comprising the steps of polishing sharp corner(s) of the surface of a...
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6339243 |
High voltage device and method for fabricating the same
The disclosed high voltage device includes a semiconductor substrate, and a first semiconductor layer formed between an underlying first insulating layer and an overlying second insulating layer...
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6335261 |
Directional CVD process with optimized etchback
A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate...
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6329288 |
Semiconductor device and manufacturing method thereof
A process of exposing the head of a metal post used with a chip size package is simplified. A first semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so...
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6326310 |
Method and system for providing shallow trench profile shaping through spacer and etching
A system and method for providing a trench in a material using semiconductor processing is disclosed. In one aspect, the method and system include (a) providing a spacer, (b) etching the material,...
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6326311 |
Microstructure producing method capable of controlling growth position of minute particle or thin and semiconductor device employing the microstructure
There is provided a microstructure producing method capable of achieving satisfactory uniformity and reproducibility of the growth position, size and density of a minute particle or thin line and...
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6319838 |
Lever arm for a scanning microscope
In a method of producing a lever arm with a tip for a scanning microscope wherein, in a wafer including a tip, a piezo-resistive resistance is implanted by means of C-MOS, a metallic layer is first...
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6319731 |
Method for manufacturing a non-volatile memory device
A nonvolatile ferroelectric memory device and a method for manufacturing the same increase capacitance by ensuring an area of a capacitor to the maximum degree and simplify process steps by...
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6319835 |
Stripping method
Disclosed are compositions useful for removing antireflective compositions from a substrate. Also disclosed are methods of removing antireflective compositions from a substrate using such...
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6319819 |
Process for passivating top interface of damascene-type Cu interconnect lines
The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized metallization patterns, e.g., of copper, in-laid in the exposed upper surface of a layer of...
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6316833 |
Semiconductor device with multilayer interconnection having HSQ film with implanted fluorine and fluorine preventing liner
A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities...
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6316795 |
Silicon-carbon emitter for silicon-germanium heterojunction bipolar transistors
The invention provides an effective means and apparatus for allowing higher operational frequencies in heterojunction bipolar transistors by trapping silicon interstitial atoms and thereby...
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6303505 |
Copper interconnect with improved electromigration resistance
Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce...
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6303526 |
Temperature controlled spin chuck
An apparatus and a method of actively controlling the temperature of a surface of a workpiece is disclosed. The apparatus includes a heat exchanger and a temperature controller thermally coupled to...
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6300250 |
Method of forming bumps for flip chip applications
A new method is provided to create metal bumps on a surface, metal contact pads have been provided in this surface. A layer of dielectric is deposited over a surface; an opening is created in the...
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6290631 |
Method for restoring an alignment mark after planarization of a dielectric layer
A method for recovering the alignment mark on a substrate to the top of a dielectric layer. The method includes the steps of forming a dielectric layer over a substrate, and then forming a cap...
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6287972 |
System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication
Chemical Mechanical Processing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometry that are not widely isolated. One limiting aspect of CMP is that...
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6281130 |
Method for developing ultra-thin resist films
There is provided a method of applying a developing liquid onto a semiconductor wafer substrate having a UTR film thereon so as to minimize unexposed film thickness loss during development. This is...
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6277194 |
Method for in-situ cleaning of surfaces in a substrate processing chamber
A method of removing contaminants from a surface in a silicon substrate processing chamber. The method includes coating the surface which has been exposed to contaminants including metal particles...
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6277751 |
Method of planarization
A method for planarizing a semiconductor wafer. An insulation layer is formed over the wafer. A spin-on-glass layer is coated over the insulation layer. Subsequently, the spin-on-glass layer is...
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6274493 |
Method for forming a via
An improved method of forming a via on a semiconductor substrate forms a conductive line thereon and then forms an inter-metal dielectric layer over the conductive line. A patterned photoresist...
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6271134 |
Apparatus for manufacturing semiconductor device method for forming HSG-polysilicon layer using same and method for forming capacitor having electrode of HSG-polysilicon layer
A semiconductor device manufacturing apparatus, an HSG-polysilicon layer forming method, and a method for forming a capacitor having the HSG-polysilicon layer as an electrode equilibrate the...
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6267817 |
Methods of forming semiconductor wafers, methods of treating semiconductor wafers to alleviate slip generation, ingots of semiconductive material, and wafers of semiconductive material
The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further...
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6265328 |
Wafer edge engineering method and device
The present invention provides an apparatus (400) (500) for abating edge material from a substrate, e.g., SOI. The apparatus includes, among other elements, a housing and a rotatable member (401)...
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6265757 |
Forming attached features on a semiconductor substrate
A method for creating attached features while controlling the depth profile between the features is presented. First the features are formed with a separating barrier between the features. The...
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6261961 |
Adhesion layer for etching of tracks in nuclear trackable materials
A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method...
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6261963 |
Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices
A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer,...
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