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7618887 |
Semiconductor device with a metal line and method of forming the same
A method of forming a metal line in a semiconductor device including forming a first insulation layer and a first etch stop layer on a conductive layer, and forming a first photosensitive layer...
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RE40983 |
Method to plate C4 to copper stud
A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer...
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7615421 |
Method for fabricating thin film transistor
The present invention relates to a method for fabricating thin film transistor, more particularly, to a method for fabricating thin film transistor which not only manufactures a polycrystalline...
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7611991 |
Technique for increasing adhesion of metallization layers by providing dummy vias
By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the...
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7608503 |
Side wall active pin memory and manufacturing method
A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side...
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7605470 |
Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices
A method for fabricating a semiconductor device. The method includes providing a semiconductor substrate including a surface region. The method forms a first interlayer dielectric overlying the...
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7601640 |
Method of manfacturing semiconductor device
A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into...
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7598172 |
Method for manufacturing semiconductor device by using dual damascene process and method for manufacturing article having communicating hole
A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first...
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7598166 |
Dielectric layers for metal lines in semiconductor chips
A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric...
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7595269 |
Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer
By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The...
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7592259 |
Methods and systems for barrier layer surface passivation
This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto barrier layer for...
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7592258 |
Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same
A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high...
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7592246 |
Method and semiconductor device having copper interconnect for bonding
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a...
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7589021 |
Copper metal interconnection with a local barrier metal layer
Embodiments relate to a method of forming a copper metal interconnection in a semiconductor device using a damascene process. In embodiments, the method may include forming a damascene pattern in...
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7588667 |
Depositing rhuthenium films using ionized physical vapor deposition (IPVD)
An iPVD system is programmed to deposit a barrier and/or seed layer using a Ru-containing material into high aspect ratio nano-size features on semiconductor substrates using a process which...
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7585768 |
Combined copper plating method to improve gap fill
A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having...
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7585766 |
Methods of manufacturing copper interconnect systems
An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner...
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7585764 |
VIA bottom contact and method of manufacturing same
A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in...
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7585762 |
Vapor deposition processes for tantalum carbide nitride materials
Embodiments of the invention generally provide methods for depositing and compositions of tantalum carbide nitride materials. The methods include deposition processes that form predetermined...
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7585687 |
Electron emitter device for data storage applications and method of manufacture
A field emission device, which among other things may be used within an ultra-high density storage system, is disclosed. The emitter device includes an emitter electrode, an extractor electrode,...
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7582564 |
Process and composition for conductive material removal by electrochemical mechanical polishing
Compositions and methods for processing a substrate having a conductive material layer disposed thereon are provided. In one embodiment, a composition for processing a substrate having a conductive...
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7582558 |
Reducing corrosion in copper damascene processes
Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through,...
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7579271 |
Method for forming low dielectric constant fluorine-doped layers
A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more...
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7576006 |
Protective self-aligned buffer layers for damascene interconnects
Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating...
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7576002 |
Multi-step barrier deposition method
A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In...
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7572650 |
Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is...
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7569937 |
Technique for forming a copper-based contact layer without a terminal metal
By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be...
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7569479 |
Method for fabricating semiconductor device
A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor...
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7569467 |
Semiconductor device and manufacturing method thereof
A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first...
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7566975 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal...
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7566664 |
Selective etching of MEMS using gaseous halides and reactive co-etchants
A method for etching a target material in the presence of a structural material with improved selectivity uses a vapor phase etchant and a co-etchant. Embodiments of the method exhibit improved...
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7563718 |
Method for forming tungsten layer of semiconductor device and method for forming tungsten wiring layer using the same
A semiconductor substrate is loaded into a reaction chamber to form a tungsten layer. A source gas including tungsten (W) is introduced into the reaction chamber to grow a crystal nucleus of the...
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7563704 |
Method of forming an interconnect including a dielectric cap having a tensile stress
An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned...
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7560381 |
Technique for metal deposition by electroless plating using an activation scheme including a substrate heating process
In an enhanced technique for electroless metal deposition, the substrate is heated to or above the operating temperature for the specific plating solution, while the plating solution may be...
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7560380 |
Chemical dissolution of barrier and adhesion layers
A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the...
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7560378 |
Method for manufacturing semiconductor device
A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough...
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7560016 |
Selectively accelerated plating of metal features
To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the...
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7557447 |
Semiconductor device and method for manufacturing same
An improved migration resistance of the interconnect is provided and a diffusion of silicon into the inside of the interconnect is suppressed. A semiconductor device includes a silicon substrate, a...
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7557035 |
Method of forming semiconductor devices by microwave curing of low-k dielectric films
The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired...
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7554199 |
Substrate for evaluation
The CMP technology is provided for a damascene wiring structure having a plural-layer wiring that is excellent in flatness and resolvability of Cu residue. An evaluation substrate is provided for...
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7553754 |
Electronic device, method of manufacture of the same, and sputtering target
In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the...
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7553430 |
Polishing slurries and methods for chemical mechanical polishing
Aqueous polishing slurries for chemical-mechanical polishing are effective for polishing copper at high polish rates. The aqueous slurries according to the present invention may include soluble...
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7550386 |
Advanced seed layers for interconnects
One embodiment of the present invention is a method for making metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a...
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7547633 |
UV assisted thermal processing
The present invention provides methods and apparatus for performing thermal processes to a semiconductor substrate. Thermal processing chambers of the present invention comprise two different...
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7544606 |
Method to implement stress free polishing
A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar...
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7544603 |
Method of fabricating silicon nitride layer and method of fabricating semiconductor device
A method of fabricating a silicon nitride layer is described. First, a substrate is provided. Then, a silicon nitride layer is formed on the substrate. The silicon nitride layer is UV-cured in an...
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7538024 |
Method of fabricating a dual-damascene copper structure
A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric...
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7531447 |
Process for forming integrated circuit comprising copper lines
An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.
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7524755 |
Entire encapsulation of Cu interconnects using self-aligned CuSiN film
A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier...
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7521362 |
Methods for the optimization of ion energy control in a plasma processing system
A method in a plasma processing system for etching a feature through a dielectric layer of a dual damascene stack on a semiconductor substrate is disclosed. The method includes placing the...
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