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7632736 |
Self-aligned contact formation utilizing sacrificial polysilicon
In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon...
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7622381 |
Semiconductor structure and the forming method thereof
The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a...
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7622380 |
Method of improving adhesion between two dielectric films
A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate...
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RE40983 |
Method to plate C4 to copper stud
A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer...
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7618892 |
Via hole forming method
A method of forming a via hole reaching a bonding pad in a wafer having an insulating film constituting a plurality of devices on the front surface of a substrate and bonding pads on each of the...
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7615448 |
Method of forming low resistance void-free contacts
A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to...
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7615490 |
Method for fabricating landing plug of semiconductor device
A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug...
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7611986 |
Dual damascene patterning method
A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further...
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7608538 |
Formation of vertical devices by electroplating
The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete...
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7608535 |
Method for forming metal contact in semiconductor device
An interlayer insulation layer is formed on a semiconductor substrate to cover a lower wiring layer that is also formed on the semiconductor substrate. A contact hole to expose a surface of the...
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7605070 |
Semiconductor device having contact plug formed in double structure by using epitaxial stack and metal layer and method for fabricating the same
Disclosed are a contact plug of a semiconductor device and a method for fabricating the same. The semiconductor device includes: an epitaxial stack formed by inserting a heteroepitaxy layer between...
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7601623 |
Method of manufacturing a semiconductor device with a gate electrode having a laminate structure
A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring....
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7598171 |
Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a...
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7585710 |
Methods of forming electronic devices having partially elevated source/drain structures
Methods of forming an electronic device may include forming a gate electrode on a semiconductor substrate, and forming first and second impurity doped regions of the semiconductor substrate on...
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7576003 |
Dual liner capping layer interconnect structure and method
A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing...
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7576004 |
Semiconductor chip and method of manufacturing semiconductor chip
A semiconductor chip includes a semiconductor substrate having a first principal surface, and having a device layer on the first principal surface in which a semiconductor device is formed, an...
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7566652 |
Electrically inactive via for electromigration reliability improvement
A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302 . A capping layer 306 is formed the metal line 304 . A second dielectric layer 308 is formed...
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7563714 |
Low resistance and inductance backside through vias and methods of fabricating same
A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside;...
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7560378 |
Method for manufacturing semiconductor device
A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough...
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7547628 |
Method for manufacturing capacitor
A method for manufacturing a capacitor includes depositing an interlayer insulating film on or above a plug connected to a switching element, forming a hole in the interlayer insulating film such...
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7537959 |
Chip stack package and manufacturing method thereof
A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting...
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7538029 |
Method of room temperature growth of SiOx on silicide as an etch stop layer for metal contact open of semiconductor devices
Silicide is protected during MC RIE etch by first forming an oxide film over the silicide and, after performing MC RIE etch, etching the oxide film. The oxide film is formed from a film of alloyed...
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7528068 |
Method for manufacturing semiconductor device
A semiconductor device has through electrodes with property as an electrode and excellent in manufacturing stability. The through electrode composed of a conductive small diameter plug and a...
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7524756 |
Process of forming a semiconductor assembly having a contact structure and contact liner
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a...
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7521806 |
Chip spanning connection
A system has a first chip having first semiconductor devices and first electrical connections, a second chip having second semiconductor devices and second electrical connections, and a third chip...
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7514362 |
Integrated circuit including sub-lithographic structures
A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes...
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7507661 |
Method of forming narrowly spaced flash memory contact openings and lithography masks
A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of...
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7504287 |
Methods for fabricating an integrated circuit
A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is...
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7501342 |
Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same
A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed...
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7494922 |
Small electrode for phase change memories
A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface...
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7485578 |
Semiconductor device
Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In...
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7485577 |
Method of forming metal line stacking structure in semiconductor device
The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on...
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7482272 |
Through chip connection
A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material...
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7479452 |
Method of forming contact plugs
A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are...
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7476613 |
Method of forming an electrical contact in a semiconductor device using an improved self-aligned contact (SAC) process
A contact for a semiconductor device is made by performing, inter alia, a CMP process on an interlayer insulation layer to expose a first hard mask layer of each conductive line. The interlayer...
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7473577 |
Integrated chip carrier with compliant interconnect
An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top side connected to the bottom side of the chip by...
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7473641 |
Method for manufacturing a semiconductor device, method for manufacturing magnetic memory, and the magnetic memory thereof
A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A...
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7473986 |
Positive-intrinsic-negative (PIN) diode semiconductor devices and fabrication methods thereof
Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface...
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7470620 |
Microcircuit fabrication and interconnection
Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric...
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7470619 |
Interconnect with high aspect ratio plugged vias
Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a...
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7470553 |
Built-in design edit structures
In an IC structure and method for debugging or adjusting the parameters of an IC circuitry, edit structures are formed in the IC device and are connected to desired portions of the IC circuitry buy...
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7470612 |
Method of forming metal wiring layer of semiconductor device
A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a...
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7465663 |
Semiconductor device fabrication method
In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, conduction failures of contacts and leaching of wiring metal into a silicon...
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7465662 |
Method of making semiconductor device
A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive...
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7459393 |
Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts
A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the...
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7456099 |
Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices
A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines,...
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7452809 |
Fabrication method of packaging substrate and packaging method using the packaging substrate
A fabrication method of a packaging substrate includes the steps of: forming a recess by etching a predetermined area of a lower surface of a substrate; depositing a seed layer on an upper surface...
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7452808 |
Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding
A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is...
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7452801 |
Metal interconnection structure of a semiconductor device having low resistance and method of fabricating the same
Provided is a metal interconnection structure of a semiconductor device, including a first metal film pattern disposed on an upper part of an insulation film of a semiconductor substrate; an...
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7453150 |
Three-dimensional face-to-face integration assembly
A via for connecting metallization layers of chips bonded in a face-to-face configuration is provided, as well as methods of fabricating the via. The via may function as an interconnection of...
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