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7713858 Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same  
A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array...
7713388 Out-of-plane spring structures on a substrate  
A structure has at least one structure component formed of a first material residing on a substrate, such that the structure is out of a plane of the substrate. A first coating of a second...
7704868 Fabrication of a micro-electromechanical system (MEMS) device from a complementary metal oxide semiconductor (CMOS)  
Methods of fabricating micro-electromechanical system devices from complementary metal oxide semiconductors (CMOS) are provided.
7704885 Semiconductor device and method for fabricating the same  
A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first...
7696078 Method for producing an electrical contact for an optoelectronic semiconductor chip  
A method for producing an electrical contact of an optoelectronic semiconductor chip (1), comprising providing a mirror layer (2), comprised of a metal or metal alloy, over the semiconductor chip;...
7692274 Reinforced semiconductor structures  
Reinforced semiconductor structures are provided. An exemplary embodiment of a reinforced semiconductor structure comprises a semiconductor wafer comprising a plurality of dielectric layers formed...
7691745 Land patterns for a semiconductor stacking structure and method therefor  
A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery...
7691697 Power composite integrated semiconductor device and manufacturing method thereof  
A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for...
7687310 Method for manufacturing phase change memory device which can stably form an interface between a lower electrode and a phase change layer  
A phase change memory device is manufactured by forming a sacrificial layer and a hard mask layer on a lower electrode; performing a first etching these layers and forming on the lower electrode a...
7674712 Patterning method for light-emitting devices  
A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to...
7659202 Triaxial through-chip connection  
A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of...
7659171 Methods and structure for forming self-aligned borderless contacts for strain engineered logic devices  
A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the...
7644496 Manufacturing method for imprinting stamper  
A manufacturing method for imprinting stamper is disclosed. The manufacturing method includes forming a plurality of concave patterns on an insulation layer, forming a stamper by filling copper in...
7645638 Stackable multi-chip package system with support structure  
A stackable multi-chip package system is provided including forming an external interconnect, having a base and a tip, and a paddle; mounting a first integrated circuit die over the paddle;...
7642188 Mixed signal integrated circuit with improved isolation  
A method for reducing an effective lateral resistance of a buried layer in an IC includes forming first and second circuit sections in a common substrate, the second circuit section being spaced...
7622384 Method of making multi-chip electronic package with reduced line skew  
A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each...
7622333 Integrated circuit package system for package stacking and manufacturing method thereof  
A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second...
7618844 Method of packaging and interconnection of integrated circuits  
A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the...
7608931 Interconnect array formed at least in part with repeated application of an interconnect pattern  
An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten...
7605085 Method of manufacturing interconnecting structure with vias  
First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including...
7605079 Manufacturing method for phase change RAM with electrode layer process  
A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used...
7595265 Semiconductor device and method for forming a metal line in the semiconductor device  
Contact resistance of a semiconductor device may be reduced, and thereby the reliability of the semiconductor device may be enhanced, when a metal line is formed in a semiconductor device...
7589008 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods  
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a...
7589018 Method of forming contact hole, method of manufacturing wiring board, method of manufacturing semiconductor device, and method of manufacturing electro-optical device  
A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and...
7575994 Semiconductor device and manufacturing method of the same  
The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film...
7566435 Nanowires and method for making the same  
A method for preparing nanowires is disclosed, which comprises the following steps: (a) providing a first precursor solution containing IIB group elements, and a second precursor solution...
7566647 Method of disposing and arranging dummy patterns  
A method of disposing dummy patterns is described, which is used for increasing the pattern density of an aluminum pad layer. A substrate is provided, and an aluminum pad material layer is formed...
7560382 Embedded interconnects, and methods for forming same  
The present invention relates to a semiconductor device comprising first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an...
7560817 Interconnect including a pliable surface and use thereof  
The present invention provides an interconnect. The interconnect comprises a pliable surface having a plurality of nanostructures disposed thereon, the pliable surface configured to allow the...
7550311 Near-field optical probe based on SOI substrate and fabrication method thereof  
Provided is near-field optical probe including: a cantilever arm support portion that is formed of a lower silicon layer of a silicon-on-insulator (SOI) substrate, the cantilever arm support...
7550382 Manufacturing method of semiconductor device, evaluation method of semiconductor device, and semiconductor device  
A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode...
7547578 Methods of processing semiconductor wafers having silicon carbide power devices thereon  
Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first...
7544598 Semiconductor device and method of manufacturing the same  
A method of manufacturing a semiconductor device, including: providing a semiconductor substrate which has a plurality of electrodes and in which a depression is formed on a side on which the...
7531442 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing  
Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film...
7531443 Method and system for fabricating semiconductor components with through interconnects and back side redistribution conductors  
A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of integrated circuits on the circuit...
7518192 Asymmetrical layout structure for ESD protection  
A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source...
7517798 Methods for forming through-wafer interconnects and structures resulting therefrom  
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer...
7517796 Method for patterning submicron pillars  
The present invention provides for a method to pattern and etch very small dimension pillars, for example in a memory array. When dimensions of pillars become very small, the photoresist pillars...
7514340 Composite integrated device and methods for forming thereof  
A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically...
7507661 Method of forming narrowly spaced flash memory contact openings and lithography masks  
A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of...
7494924 Method for forming reinforced interconnects on a substrate  
A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support...
7485490 Method of forming a stacked semiconductor package  
Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower...
7476974 Method to fabricate interconnect structures  
A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of...
7462942 Die pillar structures and a method of their formation  
A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.
7462557 Semiconductor component and method for contracting said semiconductor component  
The semiconductor component has several regularly arranged active cells (1), each comprising at least one main defining line (8). A bonding wire (18, 20) is fixed to at least one bonding surface...
7462523 Semiconductor memory device and method for manufacturing the same  
A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower...
7446038 Interlayer interconnect of three-dimensional memory and method for manufacturing the same  
An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection...
7445966 Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof  
A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over...
7442619 Method of forming substantially L-shaped silicide contact for a semiconductor device  
A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces...
7429528 Method of fabricating a pad over active circuit I.C. with meshed support structure  
An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is...