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8487439 Laminated and sintered ceramic circuit board, and semiconductor package including the circuit board  
A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a...
8486831 Semiconductor device manufacturing method  
A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the...
8481431 Method for opening one-side contact region of vertical transistor and method for fabricating one-side junction region using the same  
A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion...
8476160 Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall  
A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently...
8476742 Fluid ejection device comprising substrate contact via  
Edges of a first conductive layer (104) and a silicate glass layer (106) extend adjacent one another along a via (164) extending to a semiconductor substrate (41). An electrical conductor...
8471367 Semiconductor device and method for manufacturing semiconductor device  
A semiconductor device includes a second oxide film and a pad electrode on a first oxide film that is formed on a front surface of a semiconductor substrate, a contact electrode and a first...
8470709 Formation of metal-containing nano-particles for use as catalysts for carbon nanotube synthesis  
The present invention relates to a method for forming metal-silicide catalyst nanoparticles with controllable diameter. The method according to embodiments of the invention leads to the formation...
8466062 TSV backside processing using copper damascene interconnect technology  
Generally, the subject matter disclosed herein relates to interconnect structures used for making electrical connections between semiconductor chips in a stacked or 3D chip configuration, and...
8466566 Semiconductor device, method for manufacturing of semiconductor device, and switching circuit  
It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes...
8461037 Method for fabricating interconnections with carbon nanotubes  
A method for fabricating interconnections with carbon nanotubes of the present invention comprises the following steps: forming a dual-layer that contains a catalytic layer and an upper covering...
8461036 Multiple surface finishes for microelectronic package substrates  
Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate, masking the first area...
8461060 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles  
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating...
8455347 Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types  
Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging...
8455354 Layouts of POLY cut openings overlapping active regions  
A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an...
8450172 Non-insulating stressed material layers in a contact level of semiconductor devices  
In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements,...
8450768 Semiconductor light-emitting element and process for production thereof  
The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode...
8441112 Method of manufacturing layered chip package  
A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and...
8435876 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the...
8431474 Three dimensional multilayer circuit  
A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template...
8432031 Semiconductor die including a current routing line having non-metallic slots  
A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a...
8431485 Manufacturing method for a buried circuit structure  
A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a...
8426963 Power semiconductor package structure and manufacturing method thereof  
A power semiconductor package structure includes a carrier, a first power chip, a second power chip, a first conductive sheet, a second conductive sheet and a third conductive sheet. The first...
8420521 Method for fabricating stack structure of semiconductor packages  
A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a...
8420951 Package structure  
A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the...
8415802 Strip conductor structure for minimizing thermomechanical loads  
A semiconductor chip device including a surface on which at least one electrical contact surface is provided. A foil from an electrically insulating material is applied, especially by vacuum, to...
8415250 Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device  
A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and...
8409937 Producing transistor including multi-layer reentrant profile  
A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer, a second electrically conductive material layer, and a third...
8409924 Flexible interconnect pattern on semiconductor package  
An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package...
8404585 Preventing breakage of long metal signal conductors on semiconductor substrates  
An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than...
8404586 Manufacturing method for semiconductor device  
A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor...
8399930 Method of manufacturing a semiconductor device having a contact plug  
There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer insulation film covering the transistor; a...
8399348 Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor  
A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first...
8395257 Electronic module and method for producing an electric functional layer on a substrate by blowing powder particles of an electrically conductive material  
An electric functional layer is produced on a surface of a substrate, having at least an electronic component, particularly a semiconductor chip, provided thereof. The electric functional layer is...
8383464 Method for producing field effect transistors with a back gate and semiconductor device  
The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the...
8384226 Hybrid bump capacitor  
A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one...
8377722 Methods of forming structures with a focused ion beam for use in atomic force probing and structures for use in atomic force probing  
Methods for forming structures to use in atomic force probing of a conductive feature embedded in a dielectric layer and structures for use in atomic force probing. An insulator layer is formed on...
8377758 Thin film transistor, array substrate and method for manufacturing the same  
A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source...
8377747 Interleaf for leadframe identification  
A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe...
8372751 Method for fabricating side contact in semiconductor device  
A method for fabricating a semiconductor device includes etching a substrate to form a body separated by a trench, forming liner layers that cover sidewalls of the body, forming a sacrificial...
8373228 Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method  
A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI)...
8362617 Semiconductor device  
One embodiment provides a semiconductor device including a carrier, a first chip attached to the carrier, a structured dielectric coupled to the chip and to the carrier, and a conducting element...
8362546 Cross-point diode arrays and methods of manufacturing cross-point diode arrays  
Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on...
8358007 Integrated circuit system employing low-k dielectrics and method of manufacture thereof  
A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via...
8357607 Method for fabricating nitride-based semiconductor device having electrode on m-plane  
A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed...
8349733 Manufacturing method of substrate with through electrode  
A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode...
8344487 Stress mitigation in packaged microchips  
A packaged microchip has a lead frame with a die directly contacting at least a single, contiguous portion of the lead frame. The portion of the lead frame has a top surface forming a concavity...
8344483 Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same  
A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array...
8338828 Semiconductor package and method of testing same  
A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to...
8338291 Producing transistor including multiple reentrant profiles  
A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. A resist...
8338293 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices  
During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may...