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6107189 Method of making a local interconnect using spacer-masked contact etch  
A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface...
6100191 Method for forming self-aligned silicide layers on sub-quarter micron VLSI circuits  
The present invention discloses a method to manufacture a self-aligned silicide layer on a substrate. A metal oxide semiconductor (MOS) device and a shallow trench are fabricated in the substrate....
6100196 Method of making a copper interconnect with top barrier layer  
A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the...
6096643 Method of fabricating a semiconductor device having polysilicon line with extended silicide layer  
A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate...
6090696 Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures  
A process used to create a non-smooth, top surface topography, for a semiconductor substrate, needed to improve the adhesion between a protective molding compound, and the underlying top surface...
6087256 Method for manufacturing modified T-shaped gate electrode  
In a method for manufacturing a semiconductor device, an insulating layer is formed on a semiconductor substrate, and a refractory metal is formed layer on the insulating layer. Then, a first...
6087278 Method for fabricating semiconductor devices having an HDP-CVD oxide layer as a passivation layer  
There is provided a method for fabricating a semiconductor device, by which passivation layers are formed with good step coverage to prevent crack or void from being occurred in high aspect ratio...
6088236 Semiconductor device having a bump having a rugged side  
A semiconductor unit including a circuit board having terminal electrodes on a surface thereof and a semiconductor device having an electrode pad on a first surface, where the semiconductor device...
6087252 Dual damascene  
An improved dual damascene process is provided. By a spacer formed on sidewalls of an oxide layer, the method can make a via plug and a metal layer serving as an interconnect simultaneously form...
6083824 Borderless contact  
A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take...
6080668 Sequential build-up organic chip carrier and method of manufacture  
A method for manufacturing electronic circuit assemblies. A layer of dielectric material is attached to a layer of electrically conductive material. Vias are formed in the layer of dielectric...
6080616 Methods of fabricating memory cells with reduced area capacitor interconnect  
A memory cell is formed including an insulation region on the substrate and a transistor including a gate on the substrate and a source/drain region in the substrate disposed between the gate and...
6077773 Damascene process for reduced feature size  
Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric...
6074912 Method for forming different area vias of dynamic random access memory  
A method for forming different area vias of dynamic random access memory is disclosed. Essential points of the invention comprise spacer is only formed on gate of periphery circuit, and depth of...
6071812 Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes  
A method of fabricating a metal contact in a reduced aspect ratio contact hole. The method begins by forming a first insulating layer and a first barrier layer having a first barrier opening over...
6069060 Method of manufacturing a semiconductor device having a single crystal silicon electrode  
It is an object to obtain a semiconductor device free from a necessity of stacking a contact hole and a lower electrode, thus preventing occurrence of an error in stacking and enabling the...
6069067 Method of manufacturing a semiconductor device  
The semiconductor of this invention is provided with a first inter-layer insulating film formed on the surface of a semiconductor substrate to a first film thickness; a plurality of first wiring...
6066556 Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated  
Conductive lines are fabricated in integrated circuits by forming a groove in an insulating layer in the integrated circuit, wherein the groove has a sidewall, a base, and an upper surface. An...
6060378 Semiconductor bonding pad for better reliability  
Improved bonding pads in an integrated circuit are provided, each having a first bonding pad layer comprising a portion of a top metal layer, and a top bonding pad layer comprising a remaining...
6060347 Method for preventing damage to gate oxide from well in complementary metal-oxide semiconductor  
A method for preventing damage to a gate oxide layer from a floating well in a CMOS device includes a first via plug and a second via plug formed in a dielectric layer. The first via plug is...
6060380 Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication  
A method for etching openings in an integrated circuit uses siliconoxynitride as a hardmask layer. Because of the relatively low reflectivity of siliconoxynitride, when a photoresist layer is...
6054378 Method for encapsulating a metal via in damascene  
Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide...
6054396 Semiconductor processing method of reducing thickness depletion of a silicide layer at a junction of different underlying layers  
A semiconductor processing method of reducing thickness depletion of a nitride layer at a junction of different underlying layers includes, a) providing a substrate, the substrate comprising a...
6051496 Use of stop layer for chemical mechanical polishing of CU damascene  
A method is disclosed for forming copper damascene interconnects without the attendant CMP (chemical-mechanical polishing) dishing problem that is encountered in the art. This is accomplished by...
6048792 Method for manufacturing an interconnection structure in a semiconductor device  
A method for forming an interconnection structure in a semiconductor device includes the steps of forming a thin, first tungsten film in a via-hole by a first LPCVD process using SiH4 gas and WF6...
6046104 Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias  
Via void formation is substantially reduced or eliminated between the steps of depositing a barrier layer on a HSQ gap fill layer, and filling a through-hole with a conductive material deposited...
6043150 Method for uniform plating of dendrites  
The present invention provides a novel method for forming uniform dendrites, on circuit features that does not result in large, elongated dendrites along the edges of the circuit features. The...
6043145 Method for making multilayer wiring structure  
In a method for making a multilayer wiring structure, a second insulating film having an etching rate slower than a first insulating film is provided on the first insulating film covering a wiring...
6040243 Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion  
A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be...
6037246 Method of making a contact structure  
Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the...
6037234 Method of fabricating capacitor  
A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By...
6028005 Methods for reducing electric fields during the fabrication of integrated circuit devices  
A method for fabricating an integrated circuit device includes the steps of forming first and second conductive regions on a substrate. The second conductive region is divided into first and...
6027994 Method to fabricate a dual metal-damascene structure in a substrate  
A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is...
6028004 Process for controlling the height of a stud intersecting an interconnect  
Electrical interconnection with studs is formed by depositing conductive stud material in contact holes in a dielectric layer; patterning the conductive stud material and removing a shallow...
6025205 Apparatus and methods of forming preferred orientation-controlled platinum films using nitrogen  
Platinum film orientation-controlled to (111), (200) and/or (220) are provided by depositing the platinum film under an atmosphere containing nitrogen as well as an inert gas (Ar, Ne, Kr, Xe) on a...
6025265 Method of forming a landing pad structure in an integrated circuit  
A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a...
6025259 Dual damascene process using high selectivity boundary layers  
A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench...
6022800 Method of forming barrier layer for tungsten plugs in interlayer dielectrics  
A method of reducing tungsten plug loss in processes for fabrication for silicon-based semiconductor devices that include a tungsten plug in a high aspect ratio contact hole. The invention...
6022797 Method of manufacturing through holes in a semiconductor device  
First through holes of a relatively small diameter and second through holes of a relatively great diameter are formed in proper shapes by separate processes, respectively, in a first layer...
6015751 Self-aligned connection to underlayer metal lines through unlanded via holes  
Methods for forming via holes in inter-level dielectric layers for via connections to underlying electrodes are described. The underlying electrodes do not have electrode pads or enlarged areas of...
6013547 Process for creating a butt contact opening for a self-aligned contact structure  
A method for fabricating a memory device, using a butt contact opening, and an overlying SAC structure, to allow connection between a gate structure, and an active device region, in a...
6008114 Method of forming dual damascene structure  
A method of forming a dual damascene structure includes providing a substrate having a metallic layer already formed thereon, and then forming a dielectric layer having a top-wide/bottom-narrow...
6008125 Method of eliminating buried contact resistance in integrated circuits  
A method is disclosed for forming a buried contact within an integrated circuit ("IC"). Initially, a gate oxide layer is deposited onto a surface of a silicon substrate. A first polysilicon layer...
6002179 Bonding pad structure for integrated circuit (I)  
A bonding pad structure formed on a semiconductor substrate comprises an insulating layer, a conducting pad, a passivation layer, and a buffer layer. The insulating layer is formed on the...
5998292 Method for making three dimensional circuit integration  
The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the...
5998295 Method of forming a rough region on a substrate  
A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process...
5994779 Semiconductor fabrication employing a spacer metallization technique  
An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing...
5990001 Method of forming a semiconductor device having a critical path wiring  
Disclosed is a semiconductor device, which has: a wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, and a wiring...
5989987 Method of forming a self-aligned contact in semiconductor fabrications  
A method is provided for use in semiconductor fabrications to form a self-aligned contact (SAC) in a semiconductor device, which can help increase the contact area between the metallization layer...
5985746 Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product  
A process and resulting product are disclosed for an integrated circuit structure including two or more metal wiring levels interconnected by metal-filled vias. A first insulation layer, such as...