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6232215 Method for forming increased density for interconnection metallization  
A layer of metal is deposited on the surface of a layer of dielectric material and layer of protective material such as a thin layer of silicon oxide is provided on the layer of metal. An etch...
6228758 Method of making dual damascene conductive interconnections and integrated circuit device comprising same  
A method of forming conductive interconnections on an integrated circuit device and an integrated circuit device comprising the same is disclosed. The method is comprised of forming first and...
6221779 Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein  
A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of...
6218275 Process for forming self-aligned contact of semiconductor device  
A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the...
6218302 Method for forming a semiconductor device  
An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the...
6218271 Method of forming a landing pad on the drain and source of a MOS transistor  
This invention provides a method of forming a landing pad on the drain and source of a MOS transistor. The MOS transistor is formed on a silicon substrate of a semiconductor wafer and comprises a...
6218223 Process for producing electrode for semiconductor element and semiconductor device having the electrode  
A process is provided for fabricating a structure wherein the longitudinal direction of a base electrode and the longitudinal direction of an emitter electrode are the same. This structure is...
6214638 Bond pad functional layout on die to improve package manufacturability and assembly  
An integrated circuit package which has a staggered bond wire pattern that increases the bond finger width to pad pitch ratio of the package. The package includes a first bond shelf, a second bond...
6211071 Optimized trench/via profile for damascene filling  
In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improve reliability by voidlessly filling recesses formed in the...
6207564 Method of forming self-aligned isolated plugged contacts  
A method for preparing an SRAM or DRAM structure on a substrate with an oppositely doped well therein, a field oxide region extending above and between the well and the substrate, first and second...
6200860 Process for preventing the reverse tunneling during programming in split gate flash  
A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the...
6200889 Semiconductor bonding pad  
Improved bonding pads in an integrated circuit are provided, each having a first bonding pad layer comprising a portion of a top metal layer, and a top bonding pad layer comprising a remaining...
6200853 Method of manufacturing semiconductor device having capacitor contact holes  
A method of manufacturing a semiconductor device having capacitor contact holes. The method comprises: forming a first insulating film to cover the gate electrode and the source/drain electrodes;...
6197678 Damascene process  
A damascene process, applicable to a semiconductor substrate, with a patterned first mask layer formed thereon. A part of the substrate not covered by the first mask layer is exposed, while a...
6197681 Forming copper interconnects in dielectric materials with low constant dielectrics  
A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a...
6197682 Structure of a contact hole in a semiconductor device and method of manufacturing the same  
The present invention relates to a multilayer wiring structure for a semiconductor device which can be designed without sacrificing either a micronization or electric properties, and a...
6187658 Bond pad for a flip chip package, and method of forming the same  
A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond...
6184124 Method of making embedded wiring system  
A method of preparing a multilevel embedded wiring system for an IC comprising a first wiring formation step, a first connecting portion formation step, and a second wiring formation step, wherein...
6184118 Method for preventing the peeling of the tungsten metal after the metal-etching process  
The present invention is a method for preventing the peeling phenomena of the Tungsten metal in the integrated circuit after the metal-etching process. A semiconductor's substrate is provided. An...
6184126 Fabricating method of dual damascene  
A method of dual damascene includes forming a first conducting layer on a substrate, which already contains formed devices, and then forming a first dielectric layer and a hard material layer on...
6177733 Semiconductor device  
A semiconductor device is provided with a semiconductor substrate and five electrode pads disposed on the semiconductor substrate. Four of the electrode pads form a rectangle, and the remaining...
6174804 Dual damascene manufacturing process  
A dual damascene process for forming interconnects such as contact plugs or vias. A first metal line is formed on a substrate structure. A first metal line is formed on the substrate structure. At...
6171956 Method for improving the thermal conductivity of metal lines in integrated circuits  
The method includes forming a metal layer over a substrate. Subsequently, a discrete dot masking is deposited on the surface of the metal layer. A discrete rugged polysilicon or hemispherical...
6169022 Method of forming projection electrodes  
A method of forming projection electrodes includes the steps of mounting a resin mask on a base having pad portions on which projection electrodes should be formed, the resin mask having openings...
6169664 Selective performance enhancements for interconnect conducting paths  
In an integrated circuit, the conducting paths electrically coupling the electronic components can be fabricated to conform to conflicting physical property requirements. After formation of the...
6168985 Semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity and method of manufacturing same  
In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion...
6165886 Advanced IC bonding pad design for preventing stress induced passivation cracking and pad delimitation through stress bumper pattern and dielectric pin-on effect  
An improved metal bonding pad is disclosed which can prevent the formation of cracks during the high temperature PECVD deposition, and the subsequent annealing, of a passivation layer which is...
6162722 Unlanded via process  
A method is provided for forming an unlanded via hole that substantially solves both the problems of high resistance and via profile loss due to etching. A patterned conductor layer on a first...
6159851 Borderless vias with CVD barrier layer  
Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A...
6159774 Multi-layer interconnection layout between a chip core and peripheral devices  
An integrated circuit chip has a multi-layer input/output pad interconnection structure which allows input/output buffers to be flexibly coupled to input/output pads depending on the chip's...
6159841 Method of fabricating lateral power MOSFET having metal strap layer to reduce distributed resistance  
To reduce the distributed resistance in an integrated circuit die, a relatively thick metal strap layer is deposited on a bus or other conductive path in the top metal layer. The metal strap layer...
6156642 Method of fabricating a dual damascene structure in an integrated circuit  
A semiconductor fabrication method is provided for fabricating a dual damascene structure in a semiconductor device. By this method, a dielectric layer is first formed over a semiconductor...
6156655 Retardation layer for preventing diffusion of metal layer and fabrication method thereof  
A retardation layer of a copper damascene process and the fabrication method thereof, to replace the conventional barrier layer with a laminated layer. The laminated layer combines the...
6153506 Integrated circuit having reduced probability of wire-bond failure  
The present invention provides an improved integrated circuit technique for increasing the reliability of wire-bonds in an integrated circuit by increasing the contact angle between certain pins...
6146996 Semiconductor device with conductive via and method of making same  
A semiconductor device includes a semiconductor substrate, e.g., a part of a silicon wafer having an oxide layer disposed thereon. A metal stack is disposed over the semiconductor substrate and a...
6143595 Method for forming buried contact  
A method of forming a buried contact. A substrate has an oxide layer and a first conductive layer thereon, and an isolation region is formed in the first conductive layer, the oxide layer and the...
6140227 Method of fabricating a glue layer of contact/via  
A method of fabricating a glue layer of a contact/via. A substrate is provided and a contact/via opening is formed within a dielectric layer on the substrate to expose the substrate. A glue layer...
6136701 Contact structure for semiconductor device and the manufacturing method thereof  
A contact structure of a semiconductor device includes an impurity-doped region formed in the semiconductor substrate, a trench having a groove in the semiconductor substrate, with the groove...
6136700 Method for enhancing the performance of a contact  
A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material...
6133142 Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias  
Reliable vias are formed by providing an adequate landing area without increasing the size of the underlying feature. Embodiments include forming a lower metal feature with an ARC layer extending...
6133133 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component  
An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to...
6133141 Methods of forming electrical connections between conductive layers  
Methods of forming electrical connections between conductive layers include the steps of forming a first electrically conductive layer on a substrate and then forming a first protective layer...
6124192 Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs  
A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug...
6121135 Modified buried contact process for IC device fabrication  
A new method of forming a butted contact and a buried contact having low contact resistance in the fabrication of integrated circuits is described. A first layer of polysilicon is deposited over a...
6114243 Method to avoid copper contamination on the sidewall of a via or a dual damascene structure  
A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A...
6114240 Method for fabricating semiconductor components using focused laser beam  
A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts...
6110824 Wire shape conferring reduced crosstalk and formation methods  
Capacitive coupling, and attendant cross-talk, is reduced by increasing the distance between wire surfaces in integrated circuit applications. This is done by changing wire shape from the...
6110825 Process for forming front-back through contacts in micro-integrated electronic devices  
The process comprises the steps of: forming a through hole from the back of a semiconductor material body; forming a hole insulating layer of electrically isolating material laterally covering the...
6107109 Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate  
An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the...
6107139 Method for making a mushroom shaped DRAM capacitor  
A method of forming a capacitor for a DRAM memory cell is disclosed. The method comprises the steps of forming a crown shaped capacitor being partially filled with oxide. Next, nitride spacers and...