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6475898 Method of forming interconnectings in semiconductor devices  
A method for forming an conductive interconnection in an electronic semiconductor device includes forming a layer of insulating material on a substrate of semiconductor material having a contact...
6445001 Semiconductor device with flip-chip structure and method of manufacturing the same  
A semiconductor device has a plurality of input/output terminals formed on the inner region on a semiconductor substrate, and a plurality of die testing terminals formed on the peripheral region...
6445066 Splitting and assigning power planes  
A method for assigning signal traces to one of a plurality of power planes on a power layer of an integrated circuit package. The integrated circuit package has an integrated circuit signal...
6444573 Method of making a slot via filled dual damascene structure with a middle stop layer  
An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop...
6432812 Method of coupling capacitance reduction  
A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to...
6420756 Semiconductor device and method  
A semiconductor device (10) has a substrate (20) with a surface (26) for defining a trench (34). A control electrode (45) is disposed at the surface to activate a conduction path (50) along a...
6413880 Strongly textured atomic ridge and dot fabrication  
The present invention provides a method for producing atomic ridges on a substrate comprising: depositing a first metal on a substrate; heating the substrate to form initial nanowires of the first...
6406993 Method of defining small openings in dielectric layers  
The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask...
6403469 Method of manufacturing dual damascene structure  
A method of producing a dual damascene structure. A substrate is provided and an insulation layer is formed over the substrate. A dual damascene opening is formed in the insulation layer. A liner...
6391711 Method of forming electrical connection between stack capacitor and node location of substrate  
The present invention relates to a method of forming a contact pedestal for an electrical connection between a stack capacitor and a node location of a substrate. The present invention is...
6383821 Semiconductor device and process  
A process for manufacturing a semiconductor device includes the formation of tungsten contact plugs suitable for very small geometry devices. As part of the process a tungsten barrier layer is...
6383923 Article comprising vertically nano-interconnected circuit devices and method for making the same  
A circuit device is disclosed comprising at least two circuit layers or circuit devices vertically interconnected with a plurality of parallel and substantially equi-length nanowires disposed...
6380042 Self-aligned contact process using stacked spacers  
A self-aligned contact process is provided on a semiconductor substrate having at least two gate structures and a plurality of lightly ion-doped regions on the semiconductor substrate. Each of the...
6372626 Method of reducing step heights in integrated circuits by using dummy conductive lines, and integrated circuits fabricated thereby  
A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the...
6372631 Method of making a via filled dual damascene structure without middle stop layer  
An interconnect structure and method of forming the same in which a barrier diffusion layer/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is...
6372114 Method of forming a semiconductor device  
A method of forming a multi-layer structure over an insulating layer comprises the steps of: selectively depositing a barrier layer on a predetermined region of an insulating layer by use of a...
6365504 Self aligned dual damascene method  
A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer, comprises the steps of: forming a conductive line pattern on the insulating layer;...
6365513 Method of making a semiconductor device including testing before thinning the semiconductor substrate  
A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the...
6358845 Method for forming inter metal dielectric  
A method is disclosed for forming insulative inter metal dielectric (IMD) layers without the attendant problems of having voids, key-holes and air gaps. This is accomplished by reducing the aspect...
6358627 Rolling ball connector  
An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the...
6359342 Flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same  
A flip-chip bumping technology is proposed, which provides a flip-chip bumping structure with dedicated test pads on semiconductor chip and method of fabricating the same. The proposed flip-chip...
6358843 Method of making ultra small vias for integrated circuits  
A method of fabricating ultra small vias in insulating layers on a semiconductor substrate for an integrated circuit by a first exposure of a photoresist to line pattern with the semiconductor...
6355556 Method for fabricating transistor  
A method for fabricating a transistor having a T-shape gate. A substrate having a sacrificial layer, a metal layer and an insulating layer in turn formed thereon is provided. A photoresist layer...
6355563 Versatile copper-wiring layout design with low-k dielectric integration  
A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping...
6350675 Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects  
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias,...
6342430 Trench isolation for micromechanical devices  
An isolation process which enhances the performance of silicon micromechanical devices incorporates dielectric isolation segments within the silicon microstructure, which is otherwise composed of...
6340631 Method for laying out wide metal lines with embedded contacts/vias  
A method for laying out wide metal lines with embedded contacts/vias that has improved process window and an electronic substrate that has having such layout exposed and developed thereon are...
6340634 Method of manufacturing an assembly of conductors and a semiconductor device manufactured by means of such an assembly  
The invention relates to a method of manufacturing an assembly (100) of conductors (1), wherein a void (11) is provided in an electroconductive plate (10), within which void an island (12) is...
6337267 Method for fabricating a semiconductor memory device and the structure thereof  
A method for fabricating a semiconductor device, wherein a dual damascene metal line is formed utilising a material layer pattern. The material layer pattern has openings to define contact holes...
6335279 Method of forming contact holes of semiconductor device  
A method of forming contact holes of a semiconductor device wherein process yield is improved and manufacturing processes can be simplified. First, a plurality of gate electrodes provided with a...
6323118 Borderless dual damascene contact  
A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process...
6319823 Process for forming a borderless via in a semiconductor device  
A method is used to form a borderless via in a semiconductor device. A conductive layer, a borophosphosilicate glass (BPSG) layer and a patterned first mask layer are formed on a dielectric layer...
6319827 Integrated electronic micromodule and method for making same  
An electronic micromodule includes a support wafer, and an integrated circuit chip on the support wafer. The integrated circuit chip includes electrical connector areas, and at least one...
6313029 Method for forming multi-layer interconnection of a semiconductor device  
Disclosed is a method for forming multi-layer interconnection of semiconductor device, which allows a contact hole to be formed at a size smaller than a resolution limit of the exposing system....
6313034 Method for forming integrated circuit device structures from semiconductor substrate oxidation mask layers  
A method for forming integrated circuit device structures upon active semiconductor regions of a semiconductor substrate. The active semiconductor regions are defined by Field OXide (FOX)...
6309960 Method of fabricating a semiconductor device  
In a method for fabricating a semiconductor device, this method comprising the steps of: forming a contact hole (208) so as to cause the etching stopper (205) on the substrate (201) to be exposed;...
6309954 Methods of forming flip chip bumps and related flip chip bump constructions  
Methods of forming flip chip bumps and related flip chip bump constructions are described. In one implementation, a bump of conductive material is formed over a substrate. At least a portion of...
6287904 Two step mask process to eliminate gate end cap shortening  
Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed...
6277741 Method and planarizing polysilicon layer  
A method for planarizing a polysilicon layer is described. A polysilicon layer is etched with an oxygen-based gas and a halogen-based gas. The oxygen-based gas comprises an nitrogen oxide oxygen...
6274475 Specialized metal profile for via landing areas  
A metal feature, defined by gaps in a patterned metal layer, is formed with an inwardly tapering profile so that it is wider at the top than at the bottom. The metal feature advantageously...
6265245 Compliant interconnect for testing a semiconductor die  
A compliant interconnect for making a temporary (or permanent) electrical connection with a semiconductor die and a method for forming the interconnect are provided. The compliant interconnect...
6261908 Buried local interconnect  
A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate...
6258706 Method for fabricating a stress buffered bond pad  
A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide...
6249421 Electrostatic actuation control system  
Electrostatic actuation arrangements are disclosed comprising of at least two wafers and having electrodes formed on their facing surfaces. One of the wafers has holes in it while the other wafer...
6248665 Delamination improvement between Cu and dielectrics for damascene process  
A new method is provided to improve surface adhesion between copper surfaces and the dielectric that is deposited over these copper surfaces. The invention eliminates the formation of CuO bubbles...
6245633 Fabrication method for a double-side double-crown stacked capacitor  
A method for fabricating a stacked capacitor is described, which is applicable to the fabrication of a capacitor with a double-sided double crown bottom electrode. The first crown structure of the...
6245599 Circuit wiring system circuit wiring method semi-conductor package and semi-conductor package substrate  
The primary objective of the present invention is to select a connecting combination of the plurality of solder ball connection pads and the plurality of wire bond pads, and generate an optimum...
6245600 Method and structure for SOI wafers to avoid electrostatic discharge  
A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge...
6236102 Chip type thin film capacitor, and manufacturing method therefor  
A chip type thin film capacitor is disclosed. The contact faces between inner electrodes and outer electrodes are expanded. That is, one end portion of each of first and second electrodes 220 and...
6232157 Thin film transistors  
The specification describes thin film transistor integrated circuits wherein the TFT devices are field effect transistors with inverted structures. The interconnect levels are produced prior to...