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6759332 Method for producing dual damascene interconnections and structure produced thereby  
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming...
6737354 Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates  
An improved source/drain extension process is provided by processing steps (steps A and G) that cover the wafer and dry etching steps (steps D and I) that provide side wall spacers of poly oxide...
6734090 Method of making an edge seal for a semiconductor device  
An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing....
6723576 Disposing method for semiconductor elements  
An active-matrix type organic EL display which uses transistors with less variation of characteristics (transistors in which active layer is a single crystal semiconductor) is made on a large area...
6713387 Method for forming contact plug in semiconductor device  
The present invention provides a method for forming a contact plug in a semiconductor device capable of preventing a decrease of contact resistance and degradation of device properties due to...
6709949 Method for aligning structures on a semiconductor substrate  
In the three-dimensional integration of integrated circuits, a thinned semiconductor substrate is arranged on a second semiconductor substrate and is mechanically and electrically connected...
6709977 Integrated circuit having oversized components and method of manafacture thereof  
An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds...
6706547 Method of manufacturing a circuit device with trenches in a conductive foil  
After conductive patterns are formed on the conductive foil every block by employing isolation trenches, conductive plating layers are arranged selectively on the conductive patterns. Therefore,...
6703310 Semiconductor device and method of production of same  
A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the...
6699732 Pitch compensation in flip-chip packaging  
A flip-chip package and packaging method use a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature, such as the temperature of the chip during...
6693032 Method of forming a contact structure having an anchoring portion  
A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are...
6693031 Formation of a metallic interlocking structure  
An electronic structure including a metallic interlocking structure for bonding a conductive plated layer to metal surface, and a method of forming the electronic structure. The method provides a...
6683002 Method to create a copper diffusion deterrent interface  
Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions...
6667235 Semiconductor device and manufacturing method therefor  
An undercut portion is provided in the side surface of a wiring pattern formed over the electrode terminal forming surface of a semiconductor element so that when the top of the electrode terminal...
6660568 BiLevel metallization for embedded back end of the line structures  
MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for good MRAM performance and also for good operation of the logic...
6649504 Method for fabricating high aspect ratio electrodes  
In a method for building high aspect ratio electrodes in an electrode means (E) comprising parallel electrodes (ε1,ε2) in a dense arrangement, the electrodes are built in a repeatedly performed...
6650021 Recessed bond pad  
A recessed bond pad within an electronic device on a substrate, and associated method of fabrication. The electronic device includes N contiguous levels of interconnect metallurgy, with level N...
6645855 Method for fabricating an integrated semiconductor product  
A method fabricates an integrated semiconductor product. The first step is providing a semiconductor wafer that has preformed semiconductor components. The next step is forming at least one...
6645846 Methods of forming conductive contacts to conductive structures  
A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second...
6642146 Method of depositing copper seed on semiconductor substrates  
The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations....
6620731 Method for fabricating semiconductor components and interconnects with contacts on opposing sides  
A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the...
6610598 Surface-mounted devices of light-emitting diodes with small lens  
The present invention is a surface-mounted device of light-emitting diodes (SMD LED) whose component typically has a plane on the surface. Through the calculation of Snell's Law, most of light...
6602778 Apparatus and methods for coupling conductive leads of semiconductor assemblies  
A method and apparatus for electrically coupling bond pads on the surface of a microelectronic device. The apparatus can include a microelectronic device having at least two bond pads with a...
6599777 Method for mounting flip chip on circuit board through reliable electrical connections at low contact resistance  
A flip chip is mounted on a printed circuit board, and bump electrodes and pads are established in electrical connection, wherein sealing resin between the flip chip and the printed circuit board...
6596633 Method for manufacturing a semiconductor device  
The semiconductor device comprises a silicon substrate, a first metal pattern layer which is deposited on the silicon substrate, an inter metal dielectric which is deposited on the silicon...
6593224 Method of manufacturing a multilayer interconnect substrate  
A method of manufacturing a multilayer interconnect substrate includes providing a first interconnect layer that includes a first conductive trace, wherein the first conductive trace includes a...
6586338 Methods for creating elements of predetermined shape and apparatus using these elements  
Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a...
6566758 Current crowding reduction technique for flip chip package technology  
A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can...
6562660 Method of manufacturing the circuit device and circuit device  
After a trench 54 is formed in a first conductive foil 60A, the circuit elements are mounted, and the insulating resin is applied on the laminated conductive foil 60 as the support substrate....
6562654 Tented plated through-holes and method for fabrication thereof  
A process for tenting through-holes comprises providing a circuitized substrate having a plurality of plated through-holes, wherein the plated through-holes are tented with a polyimide material.
6559048 Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning  
Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped...
6559050 Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices  
A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSiYNZ) region providing the interface...
6559527 Process for forming cone shaped solder for chip interconnection  
A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the...
6555415 Electronic configuration with flexible bonding pads  
An electronic configuration has a first surface with electrical contacts for electrical bonding. The configuration includes at least one flexible elevation made of an insulating material that is...
6552436 Semiconductor device having a ball grid array and method therefor  
A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52)...
6548393 Semiconductor chip assembly with hardened connection joint  
A semiconductor chip assembly includes a semiconductor chip, a conductive trace, an insulative adhesive and a hardened connection joint. The conductive trace includes first and second opposing...
6541368 Metal lines of semiconductor devices and methods for forming  
Metal lines of a semiconductor device and methods of forming same are disclosed. During a damascene process filling up a metal line in an insulating film, a low-k layer is used as an insulating...
6534403 Method of making a contact and via structure  
The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed...
6531384 Method of forming a bond pad and structure thereof  
A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality...
6528350 Method for fabricating a metal plated spring structure  
Efficient methods are disclosed for fabricating metal plated spring structures in which the metal is plated onto the spring structure after release. A conductive release layer is deposited on a...
6528417 Metal patterned structure for SiN surface adhesion enhancement  
A method of improving adhesion of a surface including the following steps. A structure having an upper surface is provided. A composite anchor layer is formed over the upper surface of the...
6518161 Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die  
A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads...
6512293 Mechanically interlocking ball grid array packages and method of making  
A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features...
6498092 Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper  
A semiconductor device having a dual damascene line structure and a method for fabricating the same are disclosed. The semiconductor device and the method solve the conventional problem of a...
6498096 Borderless contact to diffusion with respect to gate conductor and methods for fabricating  
A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and...
6495448 Dual damascene process  
A process for fabricating a dual damascene structure. First, a substrate having a dielectric layer is provided. A cap layer and a mask layer with at least one trench pattern are sequentially...
6491560 Array tile system and method of making same  
A tile (10) having a plurality of grooves (22). An array of tiles (10) is assembled by placing at least two tiles (10) in generally opposing relationship to one another, with the grooves (22)...
6489688 Area efficient bond pad placement  
Embodiments of the present invention provide flip-chip bond pad arrangements that lead to a smaller increase in die size than conventional approaches. This is accomplished by using the core side...
6486054 Method to achieve robust solder bump height  
The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a...
6486056 Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level  
An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The...