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6893886 Method for processing one-dimensional nano-materials  
A method for processing one-dimensional nano-materials includes the following steps: providing a substrate (11); forming one-dimensional nano-materials (12) on the substrate, the one-dimensional...
6890846 Method for manufacturing semiconductor integrated circuit device  
Provided is a manufacturing method of a semiconductor device which comprises (a) depositing a first insulating film over a wafer, (b) forming an interconnect opening in the first insulating film,...
6890794 Flip chip with novel power and ground arrangement  
A method of forming a flip chip device comprises providing a semiconductor die having a core area and a periphery area. The periphery area includes an electrostatic discharge (ESD) structure. The...
6887744 Method of forming a thin film transistor substrate with a interconnection electrode  
A thin film transistor substrate including a semiconductor layer having a source region and a drain region, an insulating film and a gate electrode which are formed on the semiconductor layer, an...
6884669 Hatted polysilicon gate structure for improving salicide performance and method of forming the same  
Alternate methods of forming low resistance “hatted” polysilicon gate elements are provided that increase the effective area in the polysilicon gate for silicide grain growth during silicide...
6881662 Pattern formation process for an integrated circuit substrate  
A pattern formation process for an integrated circuit substrate, which is not employing the conventional method of filling resin material directly in via filling process but adapting the metal...
6875689 Method of patterning lines in semiconductor devices  
A new process is provided for the creation of sub-micron conductive lines and patterns. A conductive layer is deposited over the surface of a substrate, a sacrificial layer that differs with the...
6867121 Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated construction  
The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying...
6867132 Large line conductive pads for interconnection of stackable circuitry  
Digital circuitry, such as interconnective pads which are patterned as waffles according to the embossing methods for flexible substrates which are disclosed, so as to be especially suited for the...
6867131 Apparatus and method of increasing sram cell capacitance with metal fill  
A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an...
6849953 Microelectronic assemblies with composite conductive elements  
A microelectronic assembly includes composite conductive elements, each incorporating a core and a coating of a low-melting conductive material. The composite conductive elements interconnect...
6849514 Method of manufacturing SONOS flash memory device  
A method of manufacturing a SONOS flash memory device is disclosed. The disclosed method comprises the steps of forming a lower oxide layer, a tunnel nitride layer, a sacrificial oxide layer, and...
6846740 Wafer-level quasi-planarization and passivation for multi-height structures  
Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the...
6844230 Methods of forming capacitors and resultant capacitor structures  
Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an...
6841408 Method of alignment for buried structures formed by surface transformation of empty spaces in solid state materials  
A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are...
6828198 System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process  
A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including...
6821872 Method of making a bit line contact device  
A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact...
6822333 Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit  
According to one embodiment (500), a method of depositing an insulating layer to fill constrained spaces on an integrated circuit is disclosed. Gate structures are formed that include sidewall...
6821887 Method of forming a metal silicide gate in a standard MOS process sequence  
The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the...
6818480 Method of forming a pattern of a semiconductor device and photomask therefor  
A method of forming the patterns of a semiconductor device uses a photomask employed therein is disclosed. In a semiconductor device having a first region where a plurality of first patterns are...
6815346 Unique feature design enabling structural integrity for advanced low k semiconductor chips  
A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The...
6815337 Method to improve borderless metal line process window for sub-micron designs  
A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed....
6812130 Self-aligned dual damascene etch using a polymer  
A method for forming a dual damascene structure for a semiconductor device, in accordance with the present invention, includes providing conductive regions on a first layer, forming an interlevel...
6812128 Method of manufacturing multilayer structured semiconductor device  
A step for forming a wiring on a semiconductor substrate, a step for forming a first silicon oxide film on the semiconductor substrate having the wiring, and a step for forming an interlayer...
6808975 Method for forming a self-aligned contact hole in a semiconductor device  
A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern...
6808984 Method for forming a contact opening  
A method for forming a contact opening is provided. After forming transistors on a substrate, a stacked resist layer including a resist layer without a silicon element and a resist layer with a...
6806122 Ball grid array module  
A Plastic Ball Grid Array electronic package of the Cavity Down type for use in HF application. The present invention allows to reduce the overall thickness of the package, by tailoring the...
6803253 Method for laminating and mounting semiconductor chip  
A plurality of semiconductor chips each having an electrode surface are sequentially laminated and mounted. Initially, the electrode surfaces of the semiconductor chips are activated. Then, the...
6803286 Method of forming a local interconnect  
A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating...
6803241 Method of monitoring contact hole of integrated circuit using corona charges  
A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges...
6803300 Method of manufacturing a semiconductor device having a ground plane  
A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator...
6797615 Method of manufacturing a semiconductor device  
A method of manufacturing a semiconductor device, in which a surface (1) of a semiconductor body (2) is provided with a first metallization layer comprising conductor tracks (3, 4), among which a...
6794262 MIM capacitor structures and fabrication methods in dual-damascene structures  
A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern...
6790720 Method for fabricating a MOSFET and reducing line width of gate structure  
A method for fabricating a MOSFET is provided. The method comprises: providing a substrate, the substrate having a gate structure; forming a drain region and a source region in the substrate, the...
6784090 Semiconductor device and method for manufacturing the same  
A semiconductor device includes a lower conductive member, an upper conductive member and a conductive wire. The one end of the conductive wire is electrically connected to a semiconductor chip....
6784101 Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation  
A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice...
6784102 Laterally interconnecting structures  
A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first...
6784068 Capacitor fabrication method  
A capacitor is fabricated over a first layer having a first conductive plug formed on a substrate in a semiconductor memory. On the first layer, a silicon nitride film, a first capacitor oxide...
6784084 Method for fabricating semiconductor device capable of reducing seam generations  
The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer...
6784017 Method of creating a high performance organic semiconductor device  
A high temperature thermal annealing process creates a low resistance contact between a metal material and an organic material of an organic semiconductor device, which improves the efficiency of...
6780761 Via-first dual damascene process  
The present invention pertains to a via-first dual damascene process. A semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate is provided. The...
6780749 Method of manufacturing a semiconductor chip comprising multiple bonding pads in staggard rows on edges  
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12....
6780694 MOS transistor  
A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode...
6777260 Method of making sub-lithographic sized contact holes  
A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the...
6774037 Method integrating polymeric interlayer dielectric in integrated circuits  
A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask...
6768063 Structure and method for shadow mask electrode  
A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of...
6768142 Circuit component placement  
A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads...
6767821 Method for fabricating an interconnect line  
A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at...
6764949 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication  
A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of...
6762507 Internal circuit structure of semiconductor chip with array-type bonding pads and method of fabricating the same  
An internal circuit structure of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the semiconductor chip, a...