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7122456 Method for reduced input output area  
An input output ring for a semiconductor device is disclosed that uses power buffers having widths that vary from the widths of the input and output buffers. In one embodiment, the pitches between...
7119000 Method of manufacturing semiconductor device  
The resist film is provided on the surface of the substrate having electrodes, and openings are provided in the resist film at positions of the electrodes on the substrate. The first metal is...
7119013 Method for fabricating semiconductor device with fine patterns  
A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch...
7118938 Method for packaging a multi-chip module of a semiconductor device  
A method for packaging a multi-chip module includes the steps of: connecting connection terminals of a tape of an anisotropic conductive adhesive film, on which a circuit is patterned to bond pads...
7115504 Method of forming electrode structure for use in an integrated circuit  
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion...
7105363 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same  
A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12)...
7105451 Method for manufacturing semiconductor device  
A resist pattern formed so as to expose a wafer edge region is used to expose an edge surface region of an Si support substrate by dry etching. Next, a conductive layer constituted as wirings by...
7101792 Methods of plating via interconnects  
Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at...
7094672 Method for forming self-aligned contact in semiconductor device  
A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method includes the steps of forming a first insulating layer...
7087516 Electromigration-reliability improvement of dual damascene interconnects  
Metallic reservoirs in the form of passive or dummy vias are used on interconnects as a source or sink for electromigration material, slowing the build up of electromigration-induced mechanical...
7078331 Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same  
Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI)...
7078730 Semiconductor light-emitting device and method of manufacturing the same and mounting plate  
To offer a semiconductor light-emitting device capable of preventing a short circuit failure caused by adhesion of the solder, change of a beam shape, and decrease of a beam output. A...
7071088 Method for fabricating bulbous-shaped vias  
The present invention provides a method for fabricating bulbous-shaped vias on a substrate, having a surface, by disposing, on the substrate, a polymerizable fluid composition. A mold is placed in...
7064447 Bond pad structure comprising multiple bond pads with metal overlap  
A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad...
7064001 Method of production of semiconductor module with external connection terminal  
A method of production of a semiconductor module comprised of a semiconductor chip, external connection terminal pads for bonding with solder balls or other external connection terminals, wires...
7056813 Methods of forming backside connections on a wafer stack  
Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The...
7056645 Use of chromeless phase shift features to pattern large area line/space geometries  
Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries. The method comprises using light at a wavelength of one of 248 nm, 193 nm, or 157 nm to...
7052987 Method for fabricating a low capacitance wiring layout  
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated...
7049180 Method of fabricating a memory transistor array utilizing insulated word lines as gate electrodes  
A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate...
7045459 Thin film encapsulation of MEMS devices  
A method of manufacturing a miniature electromechanical system (MEMS) device includes the steps of forming a moving member on a first substrate such that a first sacrificial layer is disposed...
7042080 Semiconductor interconnect having compliant conductive contacts  
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor...
7037753 Non-planar surface for semiconductor chips  
A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a...
7037820 Cross-fill pattern for metal fill levels, power supply filtering, and analog circuit shielding  
A cross-fill metal fill pattern technique is provided such that portions of a metal fill pattern are patterned to accomplish a secondary function. For instance, in the exemplary embodiments, ever...
7034400 Dual damascene interconnect structure using low stress fluorosilicate insulator with copper conductors  
A metallization insulating structure, having a substrate;a substantially fluorine free insulating layer formed on the substrate, having a height, hi;a fluorine containing insulating layer formed...
7030499 Semiconductor constructions  
The invention includes methods of forming openings extending through electrically insulative layers to electrically conductive materials. In an exemplary aspect, a substrate is provided which...
7026717 Fill pattern generation for spin-on glass and related self-planarization deposition  
A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality...
7019400 Semiconductor device having multilayer interconnection structure and method for manufacturing the device  
A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor...
7018923 Composite material for producing an electric contact surface, in addition a method for creating a lubricated, corrosion-free electric contact surface  
A modification of frictional state and surface condition of an electrical contact surface to reduce the insertion forces for establishment of an electrical plug connection and also to achieve...
7015584 High force metal plated spring structure  
Lithographically defined and etched spring structures are produced by various methods such that they avoid the formation of a plated metal wedge on an underside of the spring structure after...
7012015 Wafer-level thick film standing-wave clocking  
An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points...
7008811 Method of fabricating probe for SPM having FET channel structure utilizing self-aligned fabrication  
Provided is a method of fabricating a probe for a scanning probe microscope (SPM) having a field effect transistor (FET) channel structure utilizing a self-aligned fabrication. The provided method...
7002215 Floating entrance guard for preventing electrical short circuits  
Methods and apparatuses are provided for protecting an interconnect line in a microelectromechanical system. The interconnect line is disposed over a substrate for conducting electrical signals,...
7001836 Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers  
A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features...
6998716 Diamond metal-filled patterns achieving low parasitic coupling capacitance  
Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then...
6995043 Methods for fabricating routing elements for multichip modules  
A routing element for use with a multichip module that includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those...
6982221 Method of forming 2/3F pitch high density line array  
A method of forming a ⅔F pitch high density line array, where F is the minimum line width of a photolithographic process used to accomplish the method of the invention; includes depositing a...
6979643 Interlayer connections for layered electronic devices  
In a method for forming interlayer connections, metal conducting paths in an overlaying layer and vias forming the deposit in one and the same operation. In an interlayer connection formed in this...
6972249 Use of nitrides for flip-chip encapsulation  
A hermetically-sealed semiconductor flip-chip and its method of manufacture are disclosed. The semiconductor flip-chip of the present invention is sealed with a silicon nitride layer on an active...
6969679 Fabrication of nanoscale thermoelectric devices  
In a method for fabricating a nanowire thermoelectric device, a first electrode pattern is formed on a substrate, wherein the first electrode pattern includes bottom electrodes and a first set of...
6964874 Void formation monitoring in a damascene process  
The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two...
6964879 Method of fabricating a contact  
A method for fabricating a contact is provided. First, a substrate is provided. A patterned first material layer is formed over the substrate. The first material layer is fabricated using a...
6962835 Method for room temperature metal direct bonding  
A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to...
6946332 Forming nanoscale patterned thin film metal layers  
The specification describes a contact printing technique for forming patterns of thin films with nanometer resolution over large areas. The procedure, termed here “nanotransfer printing (nTP)”,...
6933216 Fine particle film forming apparatus and method and semiconductor device and manufacturing method for the same  
After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 μm or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a...
6930042 Method for producing a semiconductor component with at least one encapsulated chip on a substrate  
A method for producing a semiconductor component includes coating a substrate with a metalization. The metalization is structured in such a way that interconnects are formed at least in an...
6930043 Method for forming DRAM cell bit line and bit line contact structure  
Disclosed is a method for forming bit line and bit line contact structure. Based on a semi-finished structure with a poly plug filled in a contact window, the method of the Invention comprises...
6916739 Structural element and process for its production including bonding through an amorphous hard layer  
A method for manufacturing structural elements provides a first part with a surface that is substantially copper and a second part with a surface of a metal. The surface of the first part is...
6913998 Vapor-deposited porous films for energy conversion  
Metallic films are grown with a “spongelike” morphology in the as-deposited condition using planar magnetron sputtering. The morphology of the deposit is characterized by metallic continuity in...
6908862 HDP-CVD dep/etch/dep process for improved deposition into high aspect ratio features  
A method of depositing a film on a substrate disposed in a substrate processing chamber. The method includes depositing a first portion of the film by forming a high density plasma from a first...
6908801 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device comprises forming a gate insulating film on a semiconductor substrate having first and second element regions, forming a mask on the entire surface...