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6245631 |
Method of forming buried bit line memory circuitry and semiconductor processing method of forming a conductive line
The invention includes methods of forming buried bit line memory circuitry and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing...
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6245672 |
Method of forming diffusion barriers for copper metallization in integrated cirucits
An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate...
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6245671 |
Semiconductor processing method of forming an electrically conductive contact plug
A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b)...
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6245653 |
Method of filling an opening in an insulating layer
The present invention is about a method for filling an opening in an insulating layer in a fast and highly reliable way and can be used to fill openings such as trenches and via holes...
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6242345 |
Batch process for forming metal plugs in a dielectric layer of a semiconductor wafer
A batch process for the high-pressure forming of metal plugs in the dielectric layers of semiconductor wafers. After holes are etched in the dielectric layer of each wafer, and a layer of a metal...
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6239027 |
Method using a photoresist residue
An improved method for photoresist residue is described. The method is used for preventing a material layer from being damaged by the photoresist residue. A semiconductor substrate is provided. An...
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6235632 |
Tungsten plug formation
In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is...
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6232221 |
Borderless vias
Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask...
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6228759 |
Method of forming an alloy precipitate to surround interconnect to minimize electromigration
An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the...
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6225213 |
Manufacturing method for contact hole
A manufacturing method for a semiconductor device includes the steps of: forming an insulating film on a silicon substrate; removing a predetermined portion of the insulating film and forming a...
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6224942 |
Method of forming an aluminum comprising line having a titanium nitride comprising layer thereon
The invention includes methods of forming aluminum containing lines having titanium nitride containing layers thereon, and preferably by physical vapor deposition. In one aspect, a first layer...
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6221757 |
Method of making a microelectronic structure
A microelectronic structure is formed on a first layer or a substrate. The first layer or substrate is formed with grooves and contact openings. A metal nitride layer of TiN or WN covers the first...
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6221770 |
Low temperature plasma-enhanced formation of integrated circuits
Using plasma enhanced chemical vapor deposition, various layers can be deposited on semiconductor substrates at low temperatures in the same reactor. When a titanium nitride film is required, a...
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6221765 |
Method for manufacturing a semiconductor device
Inside a groove are sequentially formed a barrier-metal film 3, a seed-metal film 4 and the first plating film 6. The thickness of the first plating film 6 is about 0.1 to 0.5 the width of the...
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6221766 |
Method and apparatus for processing refractory metals on semiconductor substrates
The method and apparatus for heat treating and etching refractory metal and silicides of the refractory metal include integrated multi-chamber, multi-processing of substrates to react refractory...
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6221758 |
Effective diffusion barrier process and device manufactured thereby
In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole...
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6221754 |
Method of fabricating a plug
A method of fabricating a plug etches back the first plug material layer to form a dished surface on the first plug material layer and then performs a second coverage step. A second plug material...
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6218287 |
Method of fabricating a semiconductor structure
On a substrate is provided a layered structure of a lower insulating layer, a lower etch stop layer, an upper insulating layer and an upper etch stop layer. A via hole is formed in a location above...
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6218302 |
Method for forming a semiconductor device
An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the...
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6217721 |
Filling narrow apertures and forming interconnects with a metal utilizing a crystallographically oriented liner layer
An aluminum sputtering process, particularly useful for filling vias and contacts of high aspect ratios formed through a dielectric layer and also usefull for forming interconnects that are highly...
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6211072 |
CVD Tin Barrier process with improved contact resistance
Methods of fabricating ohmic contacts and adhesion layers therefore are provided. In one aspect, a method of fabricating an ohmic contact in an opening of an insulating layer is provided....
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6211079 |
Method for fabricating interconnects of a dynamic random access memory (DRAM)
A method for fabricating interconnects of a DRAM, in which the contact windows are formed segment by segment and the contact windows are filled segment by segment to form interconnects. Also,...
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6211083 |
Use of a novel capped anneal procedure to improve salicide formation
A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first...
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6211032 |
Method for forming silicon carbide chrome thin-film resistor
A method for forming a thin-film resistor, which is composed of silicon, carbon, and chromium, is disclosed. The resistivity of the thin-film resistor, and therefore the resistance and temperature...
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6207222 |
Dual damascene metallization
The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module...
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6207568 |
Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer
A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias...
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6207557 |
Method of forming multilayer titanium nitride film by multiple step chemical vapor deposition process and method of manufacturing semiconductor device using the same
A method of forming a multilayer titanium nitride film hardly containing any Cl component by a multiple step chemical vapor deposition method, and a method of manufacturing a semiconductor device...
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6207538 |
Method for forming n and p wells in a semiconductor substrate using a single masking step
A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide...
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6204167 |
Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer
A multi-level wiring structure having: a first wiring formed on an insulating surface, the first wiring containing refractory metal as a main composition thereof; an inter-level insulating film...
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6200910 |
Selective titanium nitride strip
A strip for TiN with selectivity to TiSi 2 consisting of a water solution of H 2 O 2 with possible small amounts of NH 4 OH.
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6200895 |
Method of forming an electrical connection
The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to...
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6197685 |
Method of producing multilayer wiring device with offset axises of upper and lower plugs
A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite...
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6197668 |
Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices
In insulated-gate, field effect transistor (IGFET) devices fabricated in integrated circuits, the scaling down of the dimensions of the devices has resulted in structures with dimensions are so...
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6191021 |
Method of forming a low-resistance contact on compound semiconductor
Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface...
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6187665 |
Process for deuterium passivation and hot carrier immunity
A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The...
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6184120 |
Method of forming a buried plug and an interconnection
In a method of forming a buried plug and an interconnection over the same, a conductive film is deposited not only over a top surface of an insulation film extending over a semiconductor substrate...
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6184118 |
Method for preventing the peeling of the tungsten metal after the metal-etching process
The present invention is a method for preventing the peeling phenomena of the Tungsten metal in the integrated circuit after the metal-etching process. A semiconductor's substrate is provided. An...
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6184129 |
Low resistivity poly-silicon gate produced by selective metal growth
A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon...
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6184130 |
Silicide glue layer for W-CVD plug application
A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is...
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6177341 |
Method for forming interconnections in semiconductor devices
The present invention provides an effective rapid thermal annealing process to fill a narrow contact window and to interconnect two conductive layers in semiconductor devices. The present invention...
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6174804 |
Dual damascene manufacturing process
A dual damascene process for forming interconnects such as contact plugs or vias. A first metal line is formed on a substrate structure. A first metal line is formed on the substrate structure. At...
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6174798 |
Process for forming metal interconnect stack for integrated circuit structure
A method of making a metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed...
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6174819 |
Low temperature photoresist removal for rework during metal mask formation
A defective photoresist mask is removed from a metal layer prior to etching by low-temperature processing to minimize or substantially eliminate any resulting residue on the metal layer, thereby...
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6175156 |
Semiconductor device with improved interconnection
An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower...
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6174805 |
Titanium film forming method
In a titanium film forming method of this invention, before a titanium film is formed, the temperature in a reaction chamber for forming the titanium film is set to a temperature or more at which...
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6171954 |
Method of manufacturing self-aligned contact
A method of forming self-aligned contact comprises the steps of forming a cap layer on top of a gate structure. Then, sidewall spacers are formed on each side of the gate structure, while a...
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6169019 |
Semiconductor apparatus and manufacturing method therefor
In a method of manufacturing a semiconductor device, a titanium silicide layer is formed on a region of a diffusion layer formed in a semiconductor substrate. A silicon nitride film functioning as...
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6159851 |
Borderless vias with CVD barrier layer
Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A...
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6156646 |
Method of manufacturing semiconductor devices
A method of manufacturing a semiconductor device is provided in which a well patterned lead line structure is obtained. In one aspect of the invention, the method comprises steps of: depositing...
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6156645 |
Method of forming a metal layer on a substrate, including formation of wetting layer at a high temperature
A wetting layer is formed on a substrate at a relatively high process temperature (e.g., the temperature of the substrate and/or the temperature within a process chamber in which the wetting layer...
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