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7601636 Implementation of a metal barrier in an integrated electronic circuit  
A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal...
7572662 Method of fabricating phase change RAM including a fullerene layer  
A method of fabricating a phase change RAM (PRAM) having a fullerene layer is provided. The method of fabricating the PRAM may include forming a bottom electrode, forming an interlayer dielectric...
7534719 Method for reduction in metal dishing after CMP  
A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily...
7528066 Structure and method for metal integration  
An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of...
7528064 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads  
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality...
7510959 Method of manufacturing a semiconductor device having damascene structures with air gaps  
A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable...
7504287 Methods for fabricating an integrated circuit  
A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is...
7494921 Aluminum metal line of a semiconductor device and method of fabricating the same  
A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer...
7485162 Polishing composition  
A polishing composition of the present invention, to be used in polishing for forming wiring in a semiconductor device, includes: a specific surfactant; a silicon oxide; at least one selected from...
7476611 Semiconductor device and manufacturing method thereof  
An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24 a is formed all over the...
7473636 Method to improve time dependent dielectric breakdown  
In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level...
7459394 Methods of manufacturing semiconductor devices  
Methods of manufacturing semiconductors are disclosed. One example method includes forming a trench through a dual damascene process, depositing a barrier metal layer on the overall surface, and...
7446033 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method  
A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in...
7416985 Semiconductor device having a multilayer interconnection structure and fabrication method thereof  
A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench...
7416930 Method for producing an oxide confined semiconductor laser  
A method for producing an oxide confined semiconductor laser uses a dual platform to synchronously produce a light emitting active area and a wire bonding area on a semiconductor material and use a...
7407879 Chemical planarization performance for copper/low-k interconnect structures  
An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric...
7384865 Semiconductor device with a metal line and method of forming the same  
A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the...
7381638 Fabrication technique using sputter etch and vacuum transfer  
First material ( 106 ) is situated on the surface of a substructure ( 100 and 102 ) and in an opening ( 104 ), such as a Wench, that extends partway through the substructure. Second material (...
7375023 Method and apparatus for chemical mechanical polishing of semiconductor substrates  
Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method...
7364997 Methods of forming integrated circuitry and methods of forming local interconnects  
In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area....
7338907 Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications  
A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture...
7291525 System and method for manufacturing thin film resistors using a trench and chemical mechanical polishing  
A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film...
7255772 High pressure processing chamber for semiconductor substrate  
A high pressure chamber comprises a chamber housing, a platen, and a mechanical drive mechanism. The chamber housing comprises a first sealing surface. The platen comprises a region for holding the...
7238607 Method to minimize formation of recess at surface planarized by chemical mechanical planarization  
When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having...
7238606 Semiconductor devices and method for fabricating the same  
Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating...
7235882 Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same  
In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern...
7232757 Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device  
Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed...
7223685 Damascene fabrication with electrochemical layer removal  
The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a...
7214602 Method of forming a conductive structure  
A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the interconnect. The layer of iridium has a...
7199043 Method of forming copper wiring in semiconductor device  
Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper...
7189638 Method for manufacturing metal structure using trench  
A method for manufacturing a metal structure using a trench includes etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the...
7172963 Manufacturing method of semiconductor integrated circuit device that includes chemically and mechanically polishing two conductive layers using two polishing pads that have different properties  
In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height...
7172962 Method of manufacturing a semiconductor device  
On a substrate are sequentially formed a first interconnection 203 , a diffusion barrier film 205 and a second insulating film 207 , and on the upper surface of the second insulating film 207 ...
7129160 Method for simultaneously removing multiple conductive materials from microelectronic substrates  
A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface...
7125800 Methods for making nearly planar dielectric films in integrated circuits  
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive,...
7104869 Barrier removal at low polish pressure  
The invention generally provides methods and compositions for planarizing a substrate surface having underlying dielectric materials. Aspects of the invention provide compositions and methods using...
7101727 Passivation planarization  
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process...
7091123 Method of forming metal wiring line including using a first insulating film as a stopper film  
In a method of forming a metal wiring line, a first insulating film is formed directly or indirectly on a semiconductor substrate. A second insulating film is formed on the first insulating film. A...
7087534 Semiconductor substrate cleaning  
Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers,...
7084053 Unidirectionally conductive materials for interconnection  
A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie...
7060606 Method and apparatus for chemical mechanical polishing of semiconductor substrates  
Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method...
7033911 Adhesive of folded package  
A package includes a flexible substrate with a first region and a second region, an encapsulated die supported by the first region, and a conformable fold adhesive introduced between the...
6984581 Structural reinforcement of highly porous low k dielectric films by ILD posts  
Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as interlayer dielectrics in advanced integrated circuits such as those which...
6982226 Method of fabricating a contact with a post contact plug anneal  
The present invention provides a process for fabricating a contact plug in a semiconductor substrate having a contact opening formed therein that comprises depositing a barrier layer in the contact...
6974769 Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization  
Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so...
6964919 Low-k dielectric film with good mechanical strength  
The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a...
6960500 Semiconductor device and method of manufacturing the same including forming metal silicide gate lines and source lines  
A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating...
6949464 Contact/via force fill techniques  
An improved semiconductor device fabrication method comprises insertion of a semiconductor wafer into a high-pressure heated chamber and deposition of a low melting-point aluminum material into a...
6949457 Barrier enhancement  
A method of forming an electrically conductive via. A first electrically conductive layer is formed, and a second layer is formed on the first layer. The second layer has desired barrier layer...
6949007 System and method for multi-stage process control in film removal  
A fabricating system. A processing tool executes a film removal process on a wafer using a chemical mechanism. A metrology tool monitors surface characteristics of the wafer to obtain a measured...
Matches 1 - 50 out of 249 1 2 3 4 5 >