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7601610 |
Method for manufacturing a high integration density power MOS device
A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming,...
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7602032 |
Memory having cap structure for magnetoresistive junction and method for structuring the same
A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed...
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7557034 |
Semiconductor device and a method of manufacturing the same
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an...
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7553758 |
Method of fabricating interconnections of microelectronic device using dual damascene process
Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a...
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7553759 |
Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device may include the following. A diffusion barrier formed over a semiconductor substrate having a conductive layer. An etching stop layer formed over a diffusion barrier....
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7544617 |
Die scale control of chemical mechanical polishing
A method for control of chemical mechanical polishing of a pattern dependant non-uniform wafer surfaces in a die scale wherein the die in the wafer surface have a plurality of zones of different...
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7538025 |
Dual damascene process flow for porous low-k materials
A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over...
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7534642 |
Methods of manufacturing an image device
In methods of manufacturing an image device, a first structure including a transparent lower portion and an opaque upper portion is formed on a substrate having a photodiode. An etch stop layer...
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7534711 |
System and method for direct etching
System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a...
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7531448 |
Manufacturing method of dual damascene structure
A manufacturing method of a dual damascene structure is provided. First, a barrier layer, a first dielectric layer, a second dielectric layer, a cap layer, a metal-containing hard mask layer, a...
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7524757 |
Method for manufacturing multi-level transistor comprising forming selective epitaxial growth layer
A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer...
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7524752 |
Method of manufacturing semiconductor device
In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111 ,...
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7521357 |
Methods of forming metal wiring in semiconductor devices using etch stop layers
A method of forming a metal wiring in a semiconductor device can include forming an etch stop layer outside a contact hole formed in an insulation layer and avoiding forming the etch stop layer...
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7521348 |
Method of fabricating semiconductor device having fine contact holes
A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor...
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7507657 |
Method for fabricating storage node contact in semiconductor device
Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused...
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7504287 |
Methods for fabricating an integrated circuit
A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is...
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7459396 |
Method for thin film deposition using multi-tray film precursor evaporation system
A method for depositing a Ru metal layer on a patterned substrate from a film precursor vapor delivered from a multi-tray film precursor evaporation system. The method comprises providing a...
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7435682 |
Method of manufacturing semiconductor device
Disclosed is a method of manufacturing a semiconductor device comprising forming an insulating film above a substrate, forming a recess in the insulating film, successively forming an underlying...
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7364924 |
Silicon phosphor electroluminescence device with nanotip electrode
An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si...
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7361587 |
Semiconductor contact and nitride spacer formation system and method
The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts....
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7361605 |
System and method for removal of photoresist and residues following contact etch with a stop layer present
In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall...
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7351635 |
Method of fabricating microelectronic device using super critical fluid
Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step....
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7341937 |
Semiconductor device and method of manufacturing same
Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a...
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7335584 |
Method of using SACVD deposition and corresponding deposition reactor
A method is provided for using SACVD deposition to deposit at least one layer of dielectric material inside a deposition reactor during the fabrication of at least one semiconductor integrated...
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7335598 |
Chemical-mechanical polishing method
A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a...
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7326645 |
Methods for forming copper interconnect of semiconductor devices
Methods for forming a copper interconnect of a semiconductor device are disclosed. A disclosed method comprises forming a lower metal interconnect; sequentially depositing a capping layer, a first...
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7300840 |
MIM capacitor structure and fabricating method thereof
A method for fabricating an MIM capacitor is disclosed. First, a substrate is provided having a first dielectric layer thereon. Next at least one first damascene conductor is formed within the...
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7291553 |
Method for forming dual damascene with improved etch profiles
A method for forming a dual damascene with improved profiles including providing a semiconductor process wafer including a dielectric insulating layer and an overlying hardmask layer; forming an...
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7288476 |
Controlled dry etch of a film
The controlled etch into a substrate or thick homogeneous film is accomplished by introducing a sacrificial film to gauge the depth to which the substrate/thick film has been etched. Optical...
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7279410 |
Method for forming inlaid structures for IC interconnections
A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and...
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7271087 |
Dual damascene interconnection in semiconductor device and method for forming the same
A dual damascene interconnection in a semiconductor device is formed to be capable of preventing fluorine (F) component from being diffused through sidewalls of a via hole and a trench. The dual...
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7262120 |
Method for fabricating metal line in semiconductor device
A method for fabricating a metal line in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the...
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7256502 |
Metal interconnections for semiconductor devices including a buffer layer on a trench sidewall
A metal interconnection for an integrated circuit device is fabricated by forming a trench in an integrated circuit substrate and a via hole beneath a portion of the trench. The trench includes a...
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7253097 |
Integrated circuit system using dual damascene process
An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a...
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7235478 |
Polymer spacer formation
A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions...
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7229911 |
Adhesion improvement for low k dielectrics to conductive materials
Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing...
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7223685 |
Damascene fabrication with electrochemical layer removal
The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a...
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7214609 |
Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying...
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7202157 |
Method for forming metallic interconnects in semiconductor devices
A method for forming a metallic interconnect in a semiconductor device is disclosed. An example method forms an IDL on a substrate including predetermined devices, forms a via hole in the IDL,...
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7179732 |
Interconnection structure and fabrication method thereof
An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence...
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7176122 |
Dielectric with sidewall passivating layer
A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may...
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7163881 |
Method for forming CMOS structure with void-free dielectric film
A process for forming a void-free dielectric layer is disclosed in which adjoining gate film stacks are formed on a semiconductor substrate. Each gate film stack includes a silicide layer and a...
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7157366 |
Method of forming metal interconnection layer of semiconductor device
Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes...
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7153767 |
Chemical mechanical polishing stopper film, process for producing the same, and method of chemical mechanical polishing
A chemical mechanical polishing stopper film comprising at least one organic polymer, said film having a dielectric constant of 4 or lower, and a chemical mechanical polishing method. The chemical...
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7151053 |
Method of depositing dielectric materials including oxygen-doped silicon carbide in damascene applications
Methods are provided for depositing an oxygen-doped dielectric layer. The oxygen-doped dielectric layer may be used for a barrier layer or a hardmask. In one aspect, a method is provided for...
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7135400 |
Damascene process capable of avoiding via resist poisoning
A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k≦2.9) thereon, a SiC layer over the low-k...
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7132362 |
Semiconductor device with contacts having uniform contact resistance and method for manufacturing the same
A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same...
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7115491 |
Method for forming self-aligned contact in semiconductor device
A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating...
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7115991 |
Method for creating barriers for copper diffusion
A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the...
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7101727 |
Passivation planarization
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is subjected to a planarization process...
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