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7608536 |
Method of manufacturing contact opening
Disclosed is a method of manufacturing a semiconductor device, in which a high-temperature SOD (spin on dielectric) annealing process is performed to prevent a SOD crack, and a nitride film,...
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7605074 |
Chemical mechanical polishing and method for manufacturing semiconductor device using the same
Provided is a CMP method. According to the CMP method, an interlayer insulating layer having two or more layers is etched to form a trench and/or via hole, and a combined thickness of the two or...
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7595263 |
Atomic layer deposition of barrier materials
Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate...
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7592258 |
Metallization layer of a semiconductor device having differently thick metal lines and a method of forming the same
A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high...
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7589014 |
Semiconductor device having multiple wiring layers and method of producing the same
A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating...
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7582564 |
Process and composition for conductive material removal by electrochemical mechanical polishing
Compositions and methods for processing a substrate having a conductive material layer disposed thereon are provided. In one embodiment, a composition for processing a substrate having a conductive...
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7582558 |
Reducing corrosion in copper damascene processes
Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through,...
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7575997 |
Method for forming contact hole of semiconductor device
A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive...
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7575981 |
Method for fabricating isolation layer in semiconductor device
A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer...
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7566652 |
Electrically inactive via for electromigration reliability improvement
A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302 . A capping layer 306 is formed the metal line 304 . A second dielectric layer 308 is formed...
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7566643 |
Liquid phase deposition of contacts in programmable resistance and switching devices
A programmable resistance, chalcogenide, switching or phase-change material device includes a substrate with a plurality of stacked layers including a conducting bottom composite electrode layer,...
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7560378 |
Method for manufacturing semiconductor device
A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough...
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7557035 |
Method of forming semiconductor devices by microwave curing of low-k dielectric films
The invention provides a method of exposing low-k dielectric films to microwave radiation to cure the dielectric films. Microwave curing reduces the cure-time necessary to achieve the desired...
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7550378 |
Method of manufacturing a semiconductor device having a cell area with a high device element density
A method for manufacturing a semiconductor device including providing a semiconductor substrate including a cell area formed with relatively high device element density and a scribe line area...
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RE40790 |
Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b)...
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7544606 |
Method to implement stress free polishing
A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar...
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7541225 |
Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode
A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a...
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7538037 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes forming a predetermined structure including a first inorganic insulating film covering a copper interconnection, an organic insulating...
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7534719 |
Method for reduction in metal dishing after CMP
A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily...
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7531447 |
Process for forming integrated circuit comprising copper lines
An integrated circuit includes copper lines, wherein the crystal structure of the copper has a greater than 30% <001 > crystal orientation and a less than 20% <111> crystal orientation.
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7528059 |
Method for reducing polish-induced damage in a contact structure by forming a capping layer
By forming a capping layer after a CMP process for planarizing the surface topography of an ILD layer, any surface irregularities may be efficiently sealed, thereby reducing the risk for forming...
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7524752 |
Method of manufacturing semiconductor device
In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111 ,...
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7521348 |
Method of fabricating semiconductor device having fine contact holes
A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor...
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7510972 |
Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device
A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface...
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7507657 |
Method for fabricating storage node contact in semiconductor device
Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused...
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7504287 |
Methods for fabricating an integrated circuit
A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is...
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7494921 |
Aluminum metal line of a semiconductor device and method of fabricating the same
A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer...
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7479433 |
Method for manufacturing semiconductor device
A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a...
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7470630 |
Approach to reduce parasitic capacitance from dummy fill
An integrated circuit includes a semiconductor substrate and multiple dielectric layers stacked on the substrate. Multiple interconnect metal lines and dummy metals are embedded in the dielectric...
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7470612 |
Method of forming metal wiring layer of semiconductor device
A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a...
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7465977 |
Method for producing a packaged integrated circuit
There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity,...
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7465652 |
Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device
A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on...
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7453152 |
Device having reduced chemical mechanical planarization
The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a semiconductor wafer to reduce the...
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7432191 |
Method of forming a dual damascene structure utilizing a developable anti-reflective coating
A method of patterning a structure in a thin film on a substrate is described. A film stack on the substrate includes the thin film on the substrate, a developable anti-reflective coating (ARC)...
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7413989 |
Method of manufacturing semiconductor device
A semiconductor wafer including an underlying layer including an insulating film having at least one recess therein and a metallic material layer formed over a top surface of the underlying layer...
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7399697 |
Very low dielectric constant plasma-enhanced CVD films
The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having...
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7399671 |
Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can...
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7381638 |
Fabrication technique using sputter etch and vacuum transfer
First material ( 106 ) is situated on the surface of a substructure ( 100 and 102 ) and in an opening ( 104 ), such as a Wench, that extends partway through the substructure. Second material (...
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7375023 |
Method and apparatus for chemical mechanical polishing of semiconductor substrates
Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method...
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7371679 |
Semiconductor device with a metal line and method of forming the same
A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing...
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7371665 |
Method for fabricating shallow trench isolation layer of semiconductor device
A method for fabricating an STI layer of a semiconductor device is disclosed, to improve the integration of the semiconductor device in a method of increasing a moat area for a gate line by...
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7368383 |
Hillock reduction in copper films
A method for treating a copper surface of a semiconductor device provides exposing the copper surface to a citric acid solution after the surface is formed using CMP (chemical mechanical polishing)...
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7364997 |
Methods of forming integrated circuitry and methods of forming local interconnects
In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area....
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7348272 |
Method of fabricating interconnect
A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over...
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7338907 |
Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications
A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture...
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7327034 |
Compositions for planarization of metal-containing surfaces using halogens and halide salts
A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for...
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7323407 |
Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material
Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during...
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7316980 |
Method for forming ferrocapacitors and FeRAM devices
Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to...
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7314823 |
Chemical mechanical polishing composition and process
A composition for chemical mechanical polishing includes a slurry. A sufficient amount of a selectively oxidizing and reducing compound is provided in the composition to produce a differential...
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7303985 |
Zeolite-carbon doped oxide composite low k dielectric
A method for forming a zeolite-carbon doped oxide (CDO) composite dielectric material is herein described. Zeolite particles may be dispersed in a solvent. The zeolite solvent solution may then be...
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