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7625816 |
Method of fabricating passivation
Embodiments relate to a passivation fabricating method. In the passivation fabricating method according to embodiments, a first oxide film may be formed by repeating deposition and etching of an...
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7611985 |
Formation of holes in substrates using dewetting coatings
Methods and systems for forming holes in a substrate using dewetting coating are described herein.
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7582556 |
Circuitry component and method for forming the same
A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first...
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7579271 |
Method for forming low dielectric constant fluorine-doped layers
A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more...
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7575997 |
Method for forming contact hole of semiconductor device
A method for forming a contact hole of a semiconductor is provided. Conductive patterns are formed over a substrate. An insulation layer is formed over the substrate to bury the conductive...
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7575995 |
Method of forming fine metal pattern and method of forming metal line using the same
There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first...
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7560375 |
Gas dielectric structure forming methods
Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for...
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7550310 |
Techniques and systems for analyte detection
Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte ( 810 ) is sensed by sensors ( 820 ) that output...
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7544606 |
Method to implement stress free polishing
A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar...
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7534719 |
Method for reduction in metal dishing after CMP
A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily...
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7528066 |
Structure and method for metal integration
An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of...
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7528064 |
Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality...
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7524757 |
Method for manufacturing multi-level transistor comprising forming selective epitaxial growth layer
A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer...
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7524697 |
Method for manufactuing a semiconductor integrated circuit device
A burn-in process for a semiconductor integrated circuit device includes a first process of positioning bump electrodes of the semiconductor integrated circuit device with respect to pads of a...
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7510972 |
Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device
A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface...
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7510959 |
Method of manufacturing a semiconductor device having damascene structures with air gaps
A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable...
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7507647 |
Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously
A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon...
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7504287 |
Methods for fabricating an integrated circuit
A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is...
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7488637 |
CMOS image sensor and method for forming the same
A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are...
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7470619 |
Interconnect with high aspect ratio plugged vias
Described is a method for forming a stackable interconnect. The interconnect is formed by depositing a first contact on a substrate; depositing a seed layer (SL) on the substrate; depositing a...
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7446033 |
Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in...
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7425501 |
Semiconductor structure implementing sacrificial material and methods for making and implementing the same
A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels...
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7416985 |
Semiconductor device having a multilayer interconnection structure and fabrication method thereof
A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench...
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7407879 |
Chemical planarization performance for copper/low-k interconnect structures
An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric...
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7405154 |
Structure and method of forming electrodeposited contacts
A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of...
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7405152 |
Reducing wire erosion during damascene processing
A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of...
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7399699 |
On-die reflectance arrangements
Improved semiconductor reflectance arrangements (e.g., semiconductor devices, systems including semiconductor devices, methods, etc.).
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7399696 |
Method for high performance inductor fabrication using a triple damascene process with copper BEOL
A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric...
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7399671 |
Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can...
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7399649 |
Semiconductor light-emitting device and fabrication method thereof
An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer...
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7396768 |
Copper damascene chemical mechanical polishing (CMP) for thin film head writer fabrication
In one method and embodiment of the present invention, at least one coil layer is formed in a write head, using a two-slurry step of copper damascene chemical mechanical polishing method with a...
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7387963 |
Semiconductor wafer and process for producing a semiconductor wafer
A semiconductor wafer has an edge region with no defects larger than or equal to 0.3 μm. The wafers are produced by a process, comprising (a) providing a semiconductor wafer having a rounded and...
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7384865 |
Semiconductor device with a metal line and method of forming the same
A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the...
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7382054 |
Method for forming self-aligned contacts and local interconnects simultaneously
The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved...
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7381638 |
Fabrication technique using sputter etch and vacuum transfer
First material ( 106 ) is situated on the surface of a substructure ( 100 and 102 ) and in an opening ( 104 ), such as a Wench, that extends partway through the substructure. Second material (...
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7375023 |
Method and apparatus for chemical mechanical polishing of semiconductor substrates
Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method...
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7348272 |
Method of fabricating interconnect
A method of fabricating interconnect is described. A first dielectric layer having an opening is formed over a substrate. A metal layer is filled into the opening. A material layer is formed over...
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7338907 |
Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications
A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture...
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7317253 |
Cobalt tungsten phosphate used to fill voids arising in a copper metallization process
A semiconductor device includes a substrate, at least one layer of functional devices formed on the substrate, a first dielectric layer formed over the functional device layer and a first...
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7316971 |
Wire bond pads
A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the...
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7273775 |
Reliable and scalable virtual ground memory array formed with reduced thermal cycle
According to one exemplary embodiment, a method of fabricating a virtual ground memory array includes forming a number of polysilicon segments on a gate dielectric layer, where the gate dielectric...
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7255772 |
High pressure processing chamber for semiconductor substrate
A high pressure chamber comprises a chamber housing, a platen, and a mechanical drive mechanism. The chamber housing comprises a first sealing surface. The platen comprises a region for holding the...
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7247256 |
CMP slurry for forming aluminum film, CMP method using the slurry, and method for forming aluminum wiring using the CMP method
A first chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, and an oxide film removal retarder which reduces a removal rate of the silicon...
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7241668 |
Planar magnetic tunnel junction substrate having recessed alignment marks
A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is...
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7238606 |
Semiconductor devices and method for fabricating the same
Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating...
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7226856 |
Nano-electrode-array for integrated circuit interconnects
An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A...
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7223685 |
Damascene fabrication with electrochemical layer removal
The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a...
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7217649 |
System and method for stress free conductor removal
A system and method for forming a semiconductor in a dual damascene structure including receiving a patterned semiconductor substrate. The semiconductor substrate having a first conductive...
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7214603 |
Method for fabricating interconnect structures with reduced plasma damage
Methods to form interconnect structures utilizing sacrificial filling material layers are described herein. Utilizing the sacrificial filling material makes it possible to reduce damage to...
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7208406 |
Method for forming gate in semiconductor device
Disclosed is a method for forming a gate in a semiconductor device. The method includes the steps of: sequentially forming a gate insulation layer and an inter-layer insulation layer on a...
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