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6180506 |
Upper redundant layer for damascene metallization
A multi-film damascene metal interconnect line for a semiconductor device and the method for manufacturing the interconnect line. The interconnect line has a redundant layer film included within...
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6177338 |
Two step barrier process
A process for forming a tungsten plug structure, in a narrow diameter contact hole, has been developed. The process features the use of a composite layer, comprised on an underlying titanium layer,...
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6174804 |
Dual damascene manufacturing process
A dual damascene process for forming interconnects such as contact plugs or vias. A first metal line is formed on a substrate structure. A first metal line is formed on the substrate structure. At...
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6174798 |
Process for forming metal interconnect stack for integrated circuit structure
A method of making a metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed...
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6175156 |
Semiconductor device with improved interconnection
An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower...
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6169024 |
Process to manufacture continuous metal interconnects
A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on...
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6165894 |
Method of reliably capping copper interconnects
The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with...
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6165834 |
Method of forming capacitors, method of processing dielectric layers, method of forming a DRAM cell
The invention comprises methods of forming capacitors, methods of processing dielectric layers, and methods of forming a DRAM cell. In one implementation, a method of processing a dielectric layer...
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6159851 |
Borderless vias with CVD barrier layer
Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A...
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6159857 |
Robust post Cu-CMP IMD process
A method is provided for cleaning exposed copper surfaces in damascene structures after chemical mechanical polishing of the copper. In a first embodiment exposed copper is annealed in a forming...
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6156646 |
Method of manufacturing semiconductor devices
A method of manufacturing a semiconductor device is provided in which a well patterned lead line structure is obtained. In one aspect of the invention, the method comprises steps of: depositing...
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6153523 |
Method of forming high density capping layers for copper interconnects with improved adhesion
The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP,...
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6150270 |
Method for forming barrier layer for copper metallization
A method comprises forming a barrier layer for copper metallization, selectively forming a silicon film on a surface of copper wiring formed on the main surface of a semiconductor substrate, and...
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6150257 |
Plasma treatment of an interconnect surface during formation of an interlayer dielectric
The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance of oxidation of the upper surface of...
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6146993 |
Method for forming in-situ implanted semiconductor barrier layers
A method is provided for forming barrier layers in channel or via openings of semiconductors by using in-situ nitriding of barrier metals (Ta, Ti, or W) after they have been deposited in channel...
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6143657 |
Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby
A via is formed between a copper conductor and a second copper conductor in a thin film electronic device with a copper plug interconnecting the copper conductor and the second copper conductor....
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6143671 |
Semiconductor device manufacturing method
A semiconductor device manufacturing method comprises the steps of depositing a first insulation coating on a substrate, forming a wiring groove on the first insulation coating, depositing aluminum...
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6140223 |
Methods of forming contacts for integrated circuits using chemical vapor deposition and physical vapor deposition
A thin conductive layer is formed on a contact hole bottom and on a contact hole sidewall in an insulating layer on an integrated circuit substrate, and then both chemical vapor deposition and...
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6140222 |
Integrated circuit dielectric formation
An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped...
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6140224 |
Method of forming a tungsten plug
A dielectric layer and a polishing stop layer are respectively formed over a substrate. A glue layer composed of titanium (Ti) is formed along the surface of the dielectric layer. The Ti layer...
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6140236 |
High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring
A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then...
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6140238 |
Self-aligned copper interconnect structure and method of manufacturing same
A copper interconnect structure is formed in a semiconductor device using self-aligned copper or tungsten via pillars to connect upper and lower copper interconnect layers separated by a...
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6136707 |
Seed layers for interconnects and methods for fabricating such seed layers
One embodiment of the present invention is a method for making metallic interconnects including: (a) forming a patterned insulating layer on a substrate, the patterned insulating layer including at...
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6136691 |
In situ plasma clean for tungsten etching back
An insulating layer is formed on a semiconductor wafer. A titanium layer (Ti) is formed on the insulating layer. A titanium nitride (TiN) layer is formed on the Ti layer to act as a barrier layer....
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6136698 |
Method of increasing contact area of a contact window
A method is provided to increase the contact area of a contact window. In this method, the contact area is mainly increased by a concavity which is formed by first forming a thin oxide layer in the...
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6133136 |
Robust interconnect structure
A structure comprising a layer of copper, a barrier layer, a layer of AlCu, and a pad-limiting layer, wherein the layer of AlCu and barrier layer are interposed between the layer of copper and...
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6130156 |
Variable doping of metal plugs for enhanced reliability
A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the...
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6130154 |
Semiconductor device and fabrication process thereof
A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is...
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6124201 |
Method for manufacturing semiconductors with self-aligning vias
An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via...
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6121132 |
Method for reducing stress on collimator titanium nitride layer
A method for reducing the stress on a titanium nitride layer formed by collimator sputtering. On a semiconductor substrate, an insulated oxide layer is formed. A trench is formed in the insulated...
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6117793 |
Using silicide cap as an etch stop for multilayer metal process and structures so formed
A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a...
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6114244 |
Method for manufacturing a semiconductor device having fine contact hole with high aspect ratio
A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier method is formed on at least one portion in contact with the semiconductor substrate in the hole. A...
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6110789 |
Contact formation using two anneal steps
A method of forming a contact is provided. The method includes the steps of forming a contact hole, creating an enhanced doped region in the contact hole, annealing the enhanced doped region,...
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6103630 |
Adding SF.sub.6 gas to improve metal undercut for hardmask metal etching
A new method of etching metal lines using SF 6 gas during the overetch step to prevent undercutting of the anti-reflective coating layer is described. Semiconductor device structures are provided...
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6099701 |
AlCu electromigration (EM) resistance
A method of manufacturing a Al-Cu line stack comprised of Ti-rich TIN, TiN, Ti-rich TiN, Al-Cu, Ti-rich TiN, TiN layers. A key feature of the invention is the sputtering of the Ti-rich TiN layers...
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6100183 |
Method for fabricating a via
A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard...
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6100184 |
Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.)...
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6100188 |
Stable and low resistance metal/barrier/silicon stack structure and related process for manufacturing
A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of...
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6096648 |
Copper/low dielectric interconnect formation with reduced electromigration
A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the...
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6093966 |
Semiconductor device with a copper barrier layer and formation thereof
A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier...
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6093638 |
Method of forming an electrical contact in a substrate
A TiN x layer is formed by disposing a substrate (18) in a chamber (12). A first reactant gas (40) comprising Ti, a second reactant gas (42) and a third reactant gas (44) comprising N are...
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6080657 |
Method of reducing AlCu hillocks
A method of aluminum metallization in the manufacture of an integrated circuit device is described. An insulating layer is provided over the surface of a semiconductor substrate wherein a metal...
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6077764 |
Process for depositing high deposition rate halogen-doped silicon oxide layer
A silicon oxide film is deposited on a substrate by first introducing a process gas into a chamber. The process gas includes a gaseous source of silicon (such as silane), a gaseous source of...
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6077771 |
Method for forming a barrier layer
A procedure for forming the barrier layer includes a plasma procedure in the fabricating procedure. The procedure is that an opening is formed on a dielectric layer, which is formed over a...
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6077772 |
Methods of forming metal interconnections including thermally treated barrier layers
A method of forming a metal interconnection includes the steps of forming a first conductive layer on a substrate, and forming an insulating layer on the first conductive layer and on the...
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6077779 |
Multi-step deposition to improve the conformality of ionized PVD films
Methods are disclosed to provide a low-cost method of producing a refractory liner in submicron vias or trenches applying ionized metal plasma using physical vapor deposition (PVD). The refractory...
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6077780 |
Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure
A method for filling, with a conductive material, a high aspect ratio opening such as a via hole or a trench opening within an integrated circuit minimizes the formation of voids and seams. This...
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6071807 |
Fabrication method of semiconductor device including insulation film with decomposed organic content
A semiconductor device including an interlayer insulation film is obtained, superior in planarization, insulation characteristics, and adhesion, suitable for microminiaturization of an element, and...
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6069070 |
Multilevel interconnections of electronic components
A process for forming an electronic component carrier, the electronic carrier having routing layers parallel to an aluminum substrate and vias perpendicular to the aluminum substrate, the process...
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6069073 |
Method for forming diffusion barrier layers
An improved method for forming diffusion barrier layers for sub-micron connects in integrated circuits is disclosed. The dual diffusion barriers is easily formed according to two-step annealing...
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