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6261949 |
Method for manufacturing semiconductor device
A contact hole is formed in the first interlayer insulation film on a semiconductor substrate. While making the contact hole remaining a cavity, the second interlayer insulation film is formed on...
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6261952 |
Method of forming copper interconnects with reduced in-line diffusion
Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, is avoided or substantially reduced by selectively removing an upper portion of the inter-layer dielectric between...
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6261953 |
Method of forming a copper oxide film to etch a copper surface evenly
A method of forming a copper oxide film on a copper surface, particularly applicable to forming copper wiring interconnects in the semiconductor industry, allows copper surfaces to be etched more...
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6260266 |
Method of forming wire interconnection wire
A silicon substrate on which a silicon dioxide film having a groove is formed is placed on a sample stage disposed in a vacuum chamber. Subsequently, a titanium film and a tungsten film are...
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6262485 |
Using implants to lower anneal temperatures
A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact...
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6258712 |
Method for forming a borderless contact
A method of a self-alignment process to enhance the yield of borderless contact is described. The method provides a two-step, selective etching process, using the difference in the etching...
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6258466 |
Metallization on titanium aluminide
Disclosed is a method for in situ formation of titanium aluminide. The disclosed method is directed to overcoming voiding problems which result in conventional titanium and aluminum metal...
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6251771 |
Hydrogen passivation of chemical-mechanically polished copper-containing layers
An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the...
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6245667 |
Method of forming via
A method of forming a via. A stacked structure has a barrier layer and a metal line is formed over a substrate. Spacers capable of serving as a barrier are formed over tapering sidewalls of the...
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6242342 |
Fabrication method for a borderless via of a semiconductor device
A method for fabricating a borderless via on a semiconductor device is described in which a substrate comprising a dielectric layer is provided. A conductive layer, a barrier layer and a metal...
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6242340 |
Method for forming an interconnection in a semiconductor device
A method of forming an interconnection layer in a semiconductor device is provided that improves the mass productivity and the reliability of the interconnection by forming a sidewall spacer on the...
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6239021 |
Dual barrier and conductor deposition in a dual damascene process for semiconductors
An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via...
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6235619 |
Manufacturing method for reduced semiconductor memory device contact holes with minimal damage to device separation characteristics
A semiconductor device manufacturing method capable of coping with scale reduction of the semiconductor device and forming contact holes without deteriorating the device separation characteristics...
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6235633 |
Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process
A novel two-step chem/mech polishing process is described for making tungsten metal plugs in a low-k polymer intermetal dielectric (IMD) layer for ULSI circuits. Since the etch selectivity between...
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6235632 |
Tungsten plug formation
In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is...
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6232223 |
High integrity borderless vias with protective sidewall spacer
High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include...
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6228767 |
Non-linear circuit elements on integrated circuits
An electrical interconnection structure on an integrated circuit is provided that has a) a substrate layer; b) a diffusion barrier on the substrate layer; c) a copper layer on the diffusion...
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6228757 |
Process for forming metal interconnects with reduced or eliminated metal recess in vias
A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an...
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6228759 |
Method of forming an alloy precipitate to surround interconnect to minimize electromigration
An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the...
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6225213 |
Manufacturing method for contact hole
A manufacturing method for a semiconductor device includes the steps of: forming an insulating film on a silicon substrate; removing a predetermined portion of the insulating film and forming a...
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6225209 |
Method of fabricating crack resistant inter-layer dielectric for a salicide process
A method for fabricating a crack resistant inter-layer dielectric for a salicide process. The method includes forming an insulating layer on a provided substrate, forming a planarized inter-layer...
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6221757 |
Method of making a microelectronic structure
A microelectronic structure is formed on a first layer or a substrate. The first layer or substrate is formed with grooves and contact openings. A metal nitride layer of TiN or WN covers the first...
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6221759 |
Method for forming aligned vias under trenches in a dual damascene process
Disclosed is a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and...
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6221758 |
Effective diffusion barrier process and device manufactured thereby
In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole...
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6218283 |
Method of fabricating a multi-layered wiring system of a semiconductor device
A method of constructing a multi-layered wiring system of a semiconductor device is provided, wherein the method includes steps of: sequentially forming first and second conductive layers on a...
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6218303 |
Via formation using oxide reduction of underlying copper
Copper is the bulk interconnect metal in the manufacture of an integrated circuit in accordance with the damascene process. When copper is exposed through via apertures, carbon monoxide and...
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6218290 |
Copper dendrite prevention by chemical removal of dielectric
The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the...
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6214660 |
Capacitor for integrated circuit and its fabrication method
A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a...
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6214731 |
Copper metalization with improved electromigration resistance
Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface...
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6211065 |
Method of depositing and amorphous fluorocarbon film using HDP-CVD
The present invention provides a method of depositing an amorphous fluorocarbon film using a high bias power applied to the substrate on which the material is deposited. The invention contemplates...
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6211070 |
Peripheral structure of a chip as a semiconductor device, and manufacturing method thereof
On a surface of a semiconductor substrate within a device forming region, a MOS transistor including a gate electrode, gate oxide film and sourcedrain is formed. An insulating layer is formed on...
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6207222 |
Dual damascene metallization
The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module...
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6207568 |
Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer
A method for forming an aluminum containing conductor layer. There is first provided a substrate. There is then formed over the substrate a titanium layer employing an ionized metal plasma bias...
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6207554 |
Gap filling process in integrated circuits using low dielectric constant materials
It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of...
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6204179 |
Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with copper
Improved methods for filling openings in silicon substrates with copper and the metal interconnects so produced are provided. One method involves the use of a Ti x Al y N z barrier layer which...
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6204167 |
Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer
A multi-level wiring structure having: a first wiring formed on an insulating surface, the first wiring containing refractory metal as a main composition thereof; an inter-level insulating film...
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6197628 |
Ruthenium silicide diffusion barrier layers and methods of forming same
A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The...
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6197678 |
Damascene process
A damascene process, applicable to a semiconductor substrate, with a patterned first mask layer formed thereon. A part of the substrate not covered by the first mask layer is exposed, while a first...
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6197681 |
Forming copper interconnects in dielectric materials with low constant dielectrics
A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a...
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6194308 |
Method of forming wire line
Titanium aluminum nitrogen ("Ti--Al--N") is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti--Al--N layer serves as...
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6194316 |
Method for forming CU-thin film
A method for forming a Cu-thin film includes the steps of coating a dispersion containing Cu-containing ultrafine particles individually dispersed therein on a semiconductor substrate having...
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6191027 |
Method of forming flat wiring layer
A method of fabricating a semiconductor device include the steps of: providing a substrate having an insulating layer thereon; forming a connection hole including a first sub-hole and a second...
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6191025 |
Method of fabricating a damascene structure for copper medullization
A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second...
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6187664 |
Method for forming a barrier metallization layer
A method for forming a barrier metallization layer upon a semiconductor substrate. A semiconductor substrate is provided which has formed upon its surface a barrier metallization layer. The barrier...
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6187661 |
Method for fabricating metal interconnect structure
A method for fabricating a metal interconnect structure. A first insulating layer and a second insulating layer with a low dielectric constant are formed on a substrate in sequence. An opening is...
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6187665 |
Process for deuterium passivation and hot carrier immunity
A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The...
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6184120 |
Method of forming a buried plug and an interconnection
In a method of forming a buried plug and an interconnection over the same, a conductive film is deposited not only over a top surface of an insulation film extending over a semiconductor substrate...
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6184550 |
Ternary nitride-carbide barrier layers
A microelectronic structure including adjacent material layers susceptible of adverse interaction in contact with one another, and a barrier layer interposed between said adjacent material layers,...
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6180512 |
Single-mask dual damascene processes by using phase-shifting mask
A simplified method is disclosed for forming dual damascene patterns using a phase-shifting mask in conjunction with a single photoresist process. First, a method is descried for fabricating a...
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6180506 |
Upper redundant layer for damascene metallization
A multi-film damascene metal interconnect line for a semiconductor device and the method for manufacturing the interconnect line. The interconnect line has a redundant layer film included within...
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