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7638422 Method of manufacturing metal insulating layer in semiconductor device  
A method of forming a metal insulating layer of a semiconductor device relieves stress due to differential thermal expansion between insulating sub-layers by rounding off sharp edges formed between...
7638424 Technique for non-destructive metal delamination monitoring in semiconductor devices  
By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without...
7618888 Temperature-controlled metallic dry-fill process  
A method for performing ionized physical vapor deposition (iPVD) is described, whereby the substrate temperature can be rapidly changed to control a metal deposition process and increase the...
7601632 Method of forming a metal line of a semiconductor device  
A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating...
7595263 Atomic layer deposition of barrier materials  
Methods for processing substrate to deposit barrier layers of one or more material layers by atomic layer deposition are provided. In one aspect, a method is provided for processing a substrate...
7592250 Multilayer wiring board, manufacturing method thereof, semiconductor device, and wireless electronic device  
A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor...
7576006 Protective self-aligned buffer layers for damascene interconnects  
Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating...
7572710 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects  
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of...
7569478 Method and apparatus for manufacturing semiconductor device, control program and computer storage medium  
In a method for manufacturing a semiconductor device having a dual damascene structure, a semiconductor substrate formed by stacking a trench mask and a via hole resist mask on an insulating film...
7569479 Method for fabricating semiconductor device  
A method for fabricating a semiconductor device capable of preventing a device failure is provided. The method includes: forming an insulating layer with a contact hole on a semiconductor...
7538022 Method of manufacturing electronic circuit device  
The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an...
7517754 Methods of forming semiconductor constructions  
The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The...
7514354 Methods for forming damascene wiring structures having line and plug conductors formed from different materials  
Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection...
7514779 Multilayer build-up wiring board  
Mesh holes 35 a and 59 a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50...
7510972 Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device  
A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface...
7504699 Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections  
A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a...
7504333 Method of forming bit line of semiconductor device  
A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An...
7482264 Method of forming metal line of semiconductor device, and semiconductor device  
A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier...
7476611 Semiconductor device and manufacturing method thereof  
An interconnect trench is formed on a dielectric layer 12 and a first HSQ layer 14 formed on a semiconductor substrate, and a tantalum family barrier metal layer 24 a is formed all over the...
7468318 Method for manufacturing mold type semiconductor device  
A method for manufacturing a mold type semiconductor device is provided. The device includes a semiconductor chip having a semiconductor part and a metallic member connecting to the chip via a...
7452802 Method of forming metal wiring for high voltage element  
Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating...
7449409 Barrier layer for conductive features  
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material...
7446032 Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films  
A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper...
7439179 Healing detrimental bonds in deposited materials  
A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited...
7416985 Semiconductor device having a multilayer interconnection structure and fabrication method thereof  
A multilayer interconnection structure includes a first interlayer insulation film, a second interlayer insulation film formed over the first interlayer insulation film, an interconnection trench...
7405152 Reducing wire erosion during damascene processing  
A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of...
7402513 Method for forming interlayer insulation film  
It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming...
7396759 Protection of Cu damascene interconnects by formation of a self-aligned buffer layer  
Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit...
7378340 Method of manufacturing semiconductor device and semiconductor device  
The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric...
7375022 Method of manufacturing wiring board  
A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is...
7368379 Multi-layer interconnect structure for semiconductor devices  
An interconnect structure for a semiconductor device and its method of manufacture is provided. The interconnect structure includes a multi-layer structure having one or more stress-relief layers....
7364997 Methods of forming integrated circuitry and methods of forming local interconnects  
In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area....
7358170 Methods of forming conductive interconnects, and methods of depositing nickel  
The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which...
7341937 Semiconductor device and method of manufacturing same  
Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a...
7338884 Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device  
An interconnecting substrate for carrying a semiconductor device, comprising: an insulating layer; an interconnection set on an obverse surface of the insulating layer; an electrode which is set on...
7335991 Pattern forming structure, pattern forming method, device, electro-optical device, and electronic apparatus  
There is provided a barrier structure provided with a concave portion corresponding to a pattern formed out of a functional liquid, the barrier structure comprising: a first concave portion...
7332428 Metal interconnect structure and method  
In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric...
7329953 Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same  
A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench...
7317253 Cobalt tungsten phosphate used to fill voids arising in a copper metallization process  
A semiconductor device includes a substrate, at least one layer of functional devices formed on the substrate, a first dielectric layer formed over the functional device layer and a first...
7303988 Methods of manufacturing multi-level metal lines in semiconductor devices  
Methods of forming a multi-level metal line of a semiconductor device are disclosed. One example method includes subsequently stacking first and second metal layers, wherein a conductive etching...
7303987 Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same  
In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum...
7300867 Dual damascene interconnect structures having different materials for line and via conductors  
Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors,...
7297630 Methods of fabricating via hole and trench  
A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a...
7288475 Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner  
The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines...
7273804 Internally reinforced bond pads  
Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric...
7262126 Sealing and protecting integrated circuit bonding pads  
A metal structure ( 600 ) for a bonding pad on integrated circuit wafers, which have interconnecting metallization ( 101 ) protected by an insulating layer ( 102 ) and selectively exposed by...
7262127 Method for Cu metallization of highly reliable dual damascene structures  
The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a...
7256121 Contact resistance reduction by new barrier stack process  
The present invention provides a method for forming an interconnect on a semiconductor substrate 100 . The method includes forming an opening 230 over an inner surface of the opening 130 , the...
7256141 Interface layer between dual polycrystalline silicon layers  
A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of...
7253092 Tungsten plug corrosion prevention method using water  
Disclosed herein is a method of making integrated circuits. In one embodiment the method includes forming tungsten plugs in the integrated circuit and forming electrically conductive interconnect...
Matches 1 - 50 out of 366 1 2 3 4 5 6 7 8 >