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8153503 Protection of cavities opening onto a face of a microstructured element  
The invention relates to a method for protecting the interior of at least one cavity (4) having a portion of interest (5) and opening onto a face of a microstructured element (1), consisting of...
8138068 Method to form nanopore array  
A method of forming nanopore is provided that includes forming a first structure on a substrate, and forming a second structure overlying the first structure. An intersecting portion of the first...
8129264 Method of fabricating a semiconductor device  
A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes...
8120184 Semiconductor constructions and methods of forming layers  
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed...
8097540 Method of opening pad in semiconductor device  
A method of opening a pad in a semiconductor device. A protective film on a pad may be etched with a pad opening pattern as a mask. Dielectric heating may be performed on the pad opened by etching...
8097949 Control of localized air gap formation in an interconnect stack  
The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect...
8084352 Method of manufacturing semiconductor device  
A high-density N-type diffusion layer 116 formed in a separation area 115 makes it possible to reduce a collector current flowing through a parasitic NPN transistor 102. Thus, a normal CMOS process...
8053861 Diffusion barrier layers  
Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier...
8039392 Resistor random access memory cell with reduced active area and reduced contact areas  
A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a...
8030202 Temporary etchable liner for forming air gap  
An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor...
8026165 Process for producing air gaps in microstructures, especially of the air gap interconnect structure type for integrated circuits  
A process for producing at least one air gap in a microstructure, including supplying a microstructure having at least one gap filled with a sacrificial material that decomposes starting from a...
8022455 Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby  
In a method of fabricating a semiconductor device capable of reducing parasitic capacitance between bit lines and a semiconductor device fabricated by the method, the semiconductor device includes...
8003537 Method for the production of planar structures  
A method for the production of a planar structure is disclosed. The method comprises producing on a substrate a plurality of structures of substantially equal height, and there being a space in...
8004087 Semiconductor device with dual damascene wirings and method for manufacturing same  
A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the...
7998855 Solving via-misalignment issues in interconnect structures having air-gaps  
An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer...
7994046 Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the air gap  
A method of forming a semiconductor structure includes providing a first dielectric layer with an opening above a substrate. An exposed surface portion of the first dielectric layer in the opening...
7989337 Implementing vertical airgap structures between chip metal layers  
A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited...
7985654 Planarization stop layer in phase change memory integration  
A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an...
7977232 Semiconductor wafer including cracking stopper structure and method of forming the same  
A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend...
7960275 Method for manufacturing an interconnection structure with cavities for an integrated circuit  
A method for manufacturing a structure of electrical interconnections for an integrated circuit having levels of interconnections, the method having steps of depositing a layer of sacrificial...
7948084 Dielectric material with a reduced dielectric constant and methods of manufacturing the same  
In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material...
7947566 Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate  
A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from...
7939446 Process for reversing tone of patterns on integerated circuit and structural process for nanoscale fabrication  
A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process...
7939922 Forming compliant contact pads for semiconductor packages  
In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes...
7932172 Semiconductor chip and process for forming the same  
A semiconductor chip comprises a first MOS device, a second MOS device, a first metallization structure connected to said first MOS device, a second metallization structure connected to said second...
7915162 Method of forming damascene filament wires  
A method of forming a semiconductor device. A first dielectric layer is deposited on and in direct mechanical contact with the substrate. A first hard mask is deposited on the first dielectric...
7910473 Through-silicon via with air gap  
A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through...
7888227 Integrated circuit inductor with integrated vias  
Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over...
7883986 Methods of forming trench isolation and methods of forming arrays of FLASH memory cells  
This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is deposited and solidified within the...
7871922 Methods for forming interconnect structures that include forming air gaps between conductive structures  
A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive...
7867924 Methods of reducing impurity concentration in isolating films in semiconductor devices  
A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper...
7858480 Semiconductor device and method of fabricating the same  
A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the...
7855139 Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device  
Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a...
7847410 Interconnect of group III-V semiconductor device and fabrication method for making the same  
An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer for...
7842613 Methods of forming microelectronic packaging substrates having through-substrate vias therein  
Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned...
7842600 Methods of forming interlayer dielectrics having air gaps  
Methods of forming an interlayer dielectric having an air gap are provided including forming a first insulating layer on a semiconductor substrate. The first insulating layer defines a trench. A...
7833890 Semiconductor device having a pair of fins and method of manufacturing the same  
Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading...
7811927 Method of manufacturing metal line  
A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer...
7812451 Semiconductor device and method of manufacturing the same  
A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring...
7811924 Air gap formation and integration using a patterning cap  
Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the...
7807563 Method for manufacturing a layer arrangement and layer arrangement  
In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent...
7807564 Method and structure for low-k interlayer dielectric layer  
An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying...
7795061 Method of creating MEMS device cavities by a non-etching process  
MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One...
7790601 Forming interconnects with air gaps  
Disclosed is a process of an integration method to form an air gap in an interconnect. On top of a metal wiring layer on a semiconductor substrate is deposited a dielectric cap layer followed by a...
7772706 Air-gap ILD with unlanded vias  
A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.
7767592 Method for forming a mask pattern for ion-implantation  
A method for forming a mask pattern for ion-implantation comprises: forming a gate line pattern over a semiconductor substrate; forming a coating layer on the surface of gate line pattern;...
7767482 Microelectromechanical systems having stored charge and methods for fabricating and using same  
Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed...
7768043 Semiconductor device having high frequency components and manufacturing method thereof  
A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the...
7759243 Method for forming an on-chip high frequency electro-static discharge device  
A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than...
7759232 Method of forming damascene patterns of semiconductor devices  
A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate,...
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