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9040408 Techniques for wafer-level processing of QFN packages  
Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level...
9040407 Sidewalls of electroplated copper interconnects  
A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a...
9040409 Methods of forming solar cells and solar cell modules  
Embodiments of the present invention are directed to processes for making solar cells by simultaneously co-firing metal layers disposed both on a first and a second surface of a bifacial solar...
9041225 Integrated circuit structure having dies with connectors  
An embodiment is an integrated circuit structure including a first die attached to a second die by a first connector. The first connector includes a solder joint portion between a first...
9029257 Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts  
Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over...
9023727 Method of manufacturing semiconductor packaging  
The present disclosure is related to a method of providing a die structure for semiconductor packaging. The method includes providing a substrate with a bonding pad; forming a patterned mask layer...
9024441 Bump structure and electronic packaging solder joint structure and fabricating method thereof  
A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the...
9018750 Thin film structure for high density inductors and redistribution in wafer level packaging  
Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact...
9010618 Magnetic attachment structure  
The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a...
9006099 Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump  
A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect...
9006096 Processes and structures for IC fabrication  
The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the...
9006097 Cu pillar bump with electrolytic metal sidewall protection  
A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes...
8994171 Method and apparatus for a conductive pillar structure  
A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive...
8993432 Test structure and method of testing electrical characteristics of through vias  
A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias...
8994173 Solder bump connection and method of making  
A layer of material can protect a surface of a passivation layer against damage during a final via plug process. The protective layer can be a conductive bump limiting metallurgy (BLM) base layer...
8987130 Reactive bonding of a flip chip package  
An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by...
8987132 Double solder bumps on substrates for low temperature flip chip bonding  
Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly...
8980739 Solder collapse free bumping process of semiconductor device  
A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a...
8975757 Lead-free solder connection structure and solder ball  
Solder used for flip chip bonding inside a semiconductor package was a Sn—Pb solder such as a Pb-5Sn composition. Lead-free solders which have been studied are hard and easily form intermetallic...
8975177 Laser resist removal for integrated circuit (IC) packaging  
Embodiments of the present disclosure are directed to laser removal of resist material from integrated circuit (IC) packaging components, as well as package assemblies and systems incorporating...
8975117 Semiconductor device using diffusion soldering  
A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor...
8975176 Gold die bond sheet preform  
The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only...
8969192 Low stress substrate and formation method  
A bumped substrate is optimized to be flat post reflow. By producing the bumped substrate to be flat post reflow, device reliability is assured. More particularly, the transistor shift associated...
8962471 Bump, method for forming the bump, and method for mounting substrate having the bump thereon  
A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a...
8962470 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus  
A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by...
8956966 TSV structures and methods for forming the same  
A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the...
8951845 Methods of fabricating a flip chip package for dram with two underfill materials  
A method of fabricating a microelectronic package can include mounting a microelectronic element to a substrate with a joining material. The mounting can include bonding a front surface of the...
8946073 Phase change memory cell with large electrode contact area  
A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first...
8946912 Active area bonding compatible high current structures  
A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from...
8937008 Apparatus and method for placing solder balls  
A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist...
8937386 Chip package structure with ENIG plating  
The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad...
8928142 Apparatus related to capacitance reduction of a signal port  
In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series...
8918988 Methods for controlling wafer curvature  
Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels,...
8916972 Adhesion between post-passivation interconnect structure and polymer  
An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to...
8910853 Additives for grain fragmentation in Pb-free Sn-based solder  
In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal...
8912042 Manufacturing method for layered chip packages  
In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered...
8912668 Electrical connections for chip scale packaging  
Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first...
8906798 Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device  
A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.
8907478 Bump pad structure  
An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an...
8907489 Wiring substrate, method of manufacturing the same, and semiconductor device  
A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite...
8901726 Package on package structure and method of manufacturing the same  
A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to...
8901733 Reliable metal bumps on top of I/O pads after removal of test probe marks  
In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of...
8896118 Electronic assembly with copper pillar attach substrate  
An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of...
8883628 Electrical connection structure  
A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on...
8871629 Methods of and semiconductor devices with ball strength improvement  
In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received....
8872336 Conductive structure and method for forming the same  
A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation...
8866293 Semiconductor structure and fabrication method thereof  
A semiconductor structure includes a semiconductor chip having at least an electrode pad, a first metal layer formed on the electrode pad, a second metal layer completely formed on and in contact...
8866298 Bonded system with coated copper conductor  
A semiconductor component includes a semiconductor die and a copper-containing electrical conductor. The semiconductor die has a semiconductor device region, an aluminum-containing metal layer on...
8859414 Electronic assemblies including mechanically secured protruding bonding conductor joints  
A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an...
8853071 Electrical connectors and methods for forming the same  
A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is...