|
Match
|
Document |
Document Title |
|
|
7619295 |
Pinched poly fuse
An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the...
|
|
|
7592206 |
Fuse region and method of fabricating the same
In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern,...
|
|
|
7579266 |
Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance
When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient...
|
|
|
7576014 |
Semiconductor device and manufacturing method thereof
A semiconductor device with a fuse 3 a to be cut for a circuit modification, of which passivation film coating the uppermost wiring layer is formed in a two-layer structure including a first...
|
|
|
7575958 |
Programmable fuse with silicon germanium
A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The...
|
|
|
7572724 |
Doped single crystal silicon silicided eFuse
An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a...
|
|
|
7566594 |
Fabricating method of semiconductor device
A fuse region and a wiring region are defined on a base to form a fuse in the fuse region of the base. A first insulation film is formed on the base and the fuse. After a first contact opening is...
|
|
|
7537969 |
Fuse structure having reduced heat dissipation towards the substrate
A fuse structure ( 100 ) suitable for incorporation in an integrated circuit presents a reduced thermal conduction footprint to the substrate ( 103 ). A patterned material stack ( 102 ) is formed...
|
|
|
7534713 |
High density chalcogenide memory cells
A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed...
|
|
|
7517763 |
Semiconductor device having fuse and capacitor at the same level and method of fabricating the same
In a semiconductor device and a method of fabricating the same, a fuse and a capacitor are formed at a same level on a semiconductor substrate having a fuse area and a capacitor area. The fuse is...
|
|
|
7517762 |
Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area
A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of...
|
|
|
7510914 |
Semiconductor devices having fuses and methods of forming the same
Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box...
|
|
|
7508016 |
CMOS imager having on-chip ROM
A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing...
|
|
|
7492032 |
Fuse regions of a semiconductor memory device and methods of fabricating the same
A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer...
|
|
|
7491585 |
Electrical fuse and method of making
A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method...
|
|
|
7479447 |
Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses
A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The...
|
|
|
7470590 |
Methods of forming semiconductor constructions
The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the...
|
|
|
7462513 |
Methods for making printed fuse devices
Embodiments of the invention relate to efficient formation of improved fuses and fuse arrays, such as can be used in memory devices for example, by use of a printer that transfers material to a...
|
|
|
7442626 |
Rectangular contact used as a low voltage fuse element
A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse...
|
|
|
7439623 |
Semiconductor device having via connecting between interconnects
A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in...
|
|
|
7439102 |
Semiconductor fuse box and method for fabricating the same
A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one...
|
|
|
7425472 |
Semiconductor fuses and semiconductor devices containing the same
A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and...
|
|
|
7422972 |
On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits
An integrated circuit programmable structure ( 60 ) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements ( 70 ) in close...
|
|
|
7413936 |
Method of forming copper layers
A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends...
|
|
|
7402464 |
Fuse box of semiconductor device and fabrication method thereof
A fuse box includes a semiconductor substrate having a fuse region, and a lower line in the fuse region that has a first region and a second region. An upper line is placed on the upper part of the...
|
|
|
7397106 |
Laser fuse with efficient heat dissipation
A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and...
|
|
|
7338843 |
Method for producing an electronic component, especially a memory chip
A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least...
|
|
|
7335537 |
Method of manufacturing semiconductor device including bonding pad and fuse elements
A method of manufacturing a semiconductor device includes forming a first insulating film supported by a semiconductor substrate, forming an aluminum layer supported by the first insulating film,...
|
|
|
7334320 |
Method of making an electronic fuse with improved ESD tolerance
Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the...
|
|
|
7314815 |
Manufacturing method of one-time programmable read only memory
An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping...
|
|
|
7268068 |
Semiconductor device and manufacturing method thereof
A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer...
|
|
|
7265001 |
Methods of fabricating semiconductor devices
Disclosed are methods of fabricating a semiconductor device, by which the pad and fuse layers play their roles smoothly and to enhance a quality of a final semiconductor device. According to one...
|
|
|
7232711 |
Method and structure to prevent circuit network charging during fabrication of integrated circuits
An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or...
|
|
|
7227238 |
Integrated fuse with regions of different doping within the fuse neck
An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second...
|
|
|
7192793 |
Fused passive organic light emitting displays
An organic light emitting device display may include transverse row and column lines. In a passively driven OLED display, a fuse may be positioned between the OLED material and the row electrode....
|
|
|
7180154 |
Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same
Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth...
|
|
|
7176551 |
Fuse structure for a semiconductor device
A fuse structure for a semiconductor device is provided. The fuse structure includes a fuse layer between the upper and lower insulating layers. The fuse layer is connected to the other metal...
|
|
|
7173317 |
Electrical and thermal contact for use in semiconductor devices
An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator component, and a contact layer. The...
|
|
|
7115512 |
Methods of forming semiconductor constructions
The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the...
|
|
|
7109105 |
Methods of making semiconductor fuses
Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride...
|
|
|
7101804 |
Method for forming fuse integrated with dual damascene process
A method for forming a fuse includes forming an interconnection pattern and a fuse pattern on a substrate using a damascene process. A passivation layer is formed on a surface of the substrate over...
|
|
|
7075127 |
Single-poly 2-transistor based fuse element
An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region...
|
|
|
7067897 |
Semiconductor device
A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered...
|
|
|
7067359 |
Method of fabricating an electrical fuse for silicon-on-insulator devices
A method and apparatus for providing an electrical fuse is provided. An electrical fuse is patterned from the active layer of a semiconductor-on-insulator (SOI) wafer. One shape of the electrical...
|
|
|
7009222 |
Protective metal structure and method to protect low-K dielectric layer during fuse blow process
A method to protect a low-K IMD layer underlying a fuse link during a fuse blowing process including a guarded fuse and method for forming the same including forming a fuse portion comprising two...
|
|
|
7005727 |
Low cost programmable CPU package/substrate
A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends...
|
|
|
6984549 |
Methods of forming semiconductor fuse arrangements
The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the...
|
|
|
6982219 |
Semiconductor device with fuse box and method for fabricating the same
A semiconductor device comprises a semiconductor substrate having a bonding pad region; and a bonding pad and a fuse box formed in the bonding pad region. Thus, the chip size can be reduced and the...
|
|
|
6979601 |
Methods for fabricating fuses for use in semiconductor devices and semiconductor devices including such fuses
A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well...
|
|
|
6969869 |
Programmable resistance memory element with indirect heating
The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming...
|