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7638417 Electronic circuit with repetitive patterns formed by shadow mask vapor deposition and a method of manufacturing an electronic circuit element  
An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit...
7595229 Configurable integrated circuit capacitor array using via mask layers  
A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may...
7521349 Fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus  
The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a...
7511998 Non-volatile memory device and method of fabricating the same  
A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a...
7494910 Methods of forming semiconductor package  
The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon...
7452796 Semi-conductor device with inductive component and method of making  
An integrated circuit ( 10 ) includes a semiconductor substrate ( 11 ) that has a top surface ( 32 ) for forming a dielectric region ( 14 ) with a trench ( 40 ) and one or more adjacent cavities (...
7413981 Pitch doubled circuit layout  
In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first...
7396750 Method and structure for contacting two adjacent GMR memory bit  
A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.
7387912 Packaging of electronic chips with air-bridge structures  
A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A...
7377032 Process for producing a printed wiring board for mounting electronic components  
A printed wiring board for mounting electronic components includes an insulating layer and a wiring pattern formed on one surface of the insulating layer, wherein one end portion of a filled via 4...
7378339 Barrier for use in 3-D integration of circuits  
A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at...
7338824 Method for manufacturing FFS mode LCD  
In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching...
7335517 Multichip semiconductor device, chip therefor and method of formation thereof  
A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film...
7335583 Isolating semiconductor device structures  
An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate...
7332378 Integrated circuit memory system with dummy active region  
An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate...
7306977 Method and apparatus for facilitating signal routing within a programmable logic device  
Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for...
7294534 Interconnect layout method  
In an interconnect layout 100, the first gate pattern, the second gate pattern, the first dummy pattern, and the second dummy pattern are arranged so that, if a wavelength of a light used to expose...
7271086 Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces  
Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In one embodiment, a method includes...
7214551 Multiple gate electrode linewidth measurement and photoexposure compensation method  
A method for fabricating a semiconductor product first provides an embedded semiconductor product comprising: (1) a logic region having formed therein a logic field effect transistor device; (2) a...
7208410 Methods relating to forming interconnects  
Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component...
7202152 Semiconductor device with inductive component and method of making  
An integrated circuit ( 10 ) includes a semiconductor substrate ( 11 ) that has a top surface ( 32 ) for forming a dielectric region ( 14 ) with a trench ( 40 ) and one or more adjacent cavities (...
7199035 Interconnect junction providing reduced current crowding and method of manufacturing same  
Disclosed herein are a junction where electrical interconnects on a semiconductor substrate intersect and a method of manufacturing a junction where electrical interconnects on a semiconductor...
7163883 Edge seal for a semiconductor device  
An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The...
7148135 Method of designing low-power semiconductor integrated circuit  
A branching point on a wire is detected in the layout results S 101 . A delay amount of a route with a dummy buffer being inserted on a wire subsequent to the branching point S 102 and that of the...
7129157 Method for fabricating an integrated circuit  
In an integrated circuit having a first circuit part and at least one second circuit part, which is assigned to a specific functionality of the first circuit part, on one and the same silicon...
7067412 Semiconductor device and method of manufacturing the same  
The present invention provides a semiconductor device including a plurality of wirings or conductive film patterns formed on a semiconductor substrate, and clearances are provided between the...
7054052 Adhesive sacrificial bonding of spatial light modulators  
A method of combining components to form an integrated device, wherein at least one first component is provided on a first surface of a sacrificial substrate, and at least one second component is...
7045392 Semiconductor device and method of fabrication thereof, semiconductor module, circuit board, and electronic equipment  
A method of fabricating a semiconductor device comprises the steps of: preparing a tape carrier 10 on which is formed lines of a plurality of bonding portions 14 across the width thereof, in a...
7042066 Dual-trench isolated crosspoint memory array  
A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si...
7012015 Wafer-level thick film standing-wave clocking  
An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points...
7001834 Integrated circuit and method of manufacturing an integrated circuit and package  
A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement...
6989297 Variable thickness pads on a substrate surface  
An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating...
6943056 Semiconductor device manufacturing method and electronic equipment using same  
A method of manufacturing semiconductor devices includes the following steps. That is, a support board is adhered to a rear surface of a substrate proper which has a plurality of circuit element...
6933611 Selective solder bump application  
Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can...
6921713 Semiconductor chip package with interconnect structure  
An active microelectronic element such as a semiconductor chip or wafer is bonded to an interconnect element having substantially the same coefficient of thermal expansion as the active element...
6917459 MEMS device and method of forming MEMS device  
A method of forming a MEMS device includes providing a substructure including a base material and at least one conductive layer formed on a first side of the base material, forming a dielectric...
6913988 Methods for fabricating semiconductor device test apparatus that include protective structures for intermediate conductive elements  
A method for fabricating apparatus for testing semiconductor devices includes forming protective structures for bond wires or other intermediate conductive elements thereof by sequentially...
6913989 Method of exposing a semiconductor integrated circuit including device regions and global routing region  
In a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate, the principal plane of the substrate is partitioned into a plurality of device...
6905967 Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems  
In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An...
6897135 Method for fabricating metal interconnections  
In the present method for fabricating metal interconnections, a Ni film is deposited on an insulating substrate by electroless plating, and a photoresist film is formed in a specified pattern on...
6885044 Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates  
In a nonvolatile memory array in which each cell ( 110 ) has two floating gates ( 160 ), for any two consecutive memory cells, one source/drain region ( 174 ) of one of the cells and one...
6864123 Memory device and manufacturing method therefor  
A technique for manufacturing memory devices which can easily manufacture ROM semiconductors having various write patterns at lower cost in a short period of time is disclosed. Since a simple...
6855608 Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance  
A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a...
6803241 Method of monitoring contact hole of integrated circuit using corona charges  
A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges...
6803300 Method of manufacturing a semiconductor device having a ground plane  
A semiconductor device includes at least first and second lower layer wirings provided on a surface of an insulator on a semiconductor substrate, a first interlayer film provided on the insulator...
6784061 Process to improve the Vss line formation for high density flash memory and related structure associated therewith  
One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the...
6780745 Semiconductor integrated circuit and method of manufacturing the same  
An IC chip comprises a chip peripheral portion and a core macro portion. The chip peripheral portion is made up of a plurality of I/O buffers each of which serves as an interface between the IC...
6777314 Method of forming electrolytic contact pads including layers of copper, nickel, and gold  
A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is...
6770493 Integrated circuit package capable of operating in multiple orientations  
An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a...
6764936 Mechanical landing pad formed on the underside of a MEMS device  
A device having a landing pad structure on an underside of a device and method for fabricating same. The device is formed from a device layer with at least one landing pad protruding from an...
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