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9012270 Metal layer enabling directed self-assembly semiconductor layout designs  
Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed...
8987923 Semiconductor seal ring  
Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor...
8928119 Three dimensional structure memory  
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately...
8912088 Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate  
The present invention provides a transfer substrate for transferring a metal wiring material to a transfer-receiving object, the transfer substrate comprising a substrate, at least one metal...
8900929 Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation  
A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the...
8877628 Methods of forming nano-scale pores, nano-scale electrical contacts, and memory devices including nano-scale electrical contacts, and related structures and devices  
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of...
8871627 Semiconductor device having low dielectric insulating film and manufacturing method of the same  
A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films...
8865585 Method of forming post passivation interconnects  
A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric...
8865583 Manufacturing method of a semiconductor device and method for creating a layout thereof  
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial...
8866193 Method for fabricating a monolithic integrated composite group III-V and group IV semiconductor device  
According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor...
8846444 Semiconductor package and method for manufacturing the same  
A semiconductor package includes a semiconductor chip having a first surface, on which an electrode pad is arranged, and a second surface which is the other side of the semiconductor chip, an...
8824114 Monitor circuit for determining the lifetime of a semiconductor device  
A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor...
8815729 Methods of forming structures on an integrated circuit product  
One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material,...
8809180 Producing SiC packs on a wafer plane  
A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a...
8803314 Hermetic packaging of integrated circuit components  
A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit...
8759207 Semiconductor structure and method for making same  
One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the...
8741762 Through silicon via dies and packages  
A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask...
8741737 Three-dimensional wafer stacking with vertical interconnects  
Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable...
8741771 Reducing wire erosion during damascene processing  
A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of...
8704353 Thermal management of stacked semiconductor chips with electrically non-functional interconnects  
A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first...
8697563 Method for forming semiconductor device having multiple active layer structure  
A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer...
8691682 Semiconductor device and method for forming the same  
Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one...
8689163 Semiconductor apparatus capable of error revision using pin extension technique and design method therefor  
A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At...
8673725 Multilayer sidewall spacer for seam protection of a patterned structure  
A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a...
8673760 Methods of forming structures on an integrated circuit product  
One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material,...
8664106 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the...
8664759 Integrated circuit with heat conducting structures for localized thermal control  
An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on...
8664125 Highly selective spacer etch process with reduced sidewall spacer slimming  
A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process...
8658526 Methods for increased array feature density  
A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers...
8642460 Semiconductor switching device and method of making the same  
A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top...
8633099 Method for forming interlayer connectors in a three-dimensional stacked IC device  
A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings...
8633104 Methods of manufacturing three-dimensional semiconductor devices  
According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of...
8629066 Liner formation in 3DIC structures  
An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The...
8629542 Three dimensional structure memory  
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately...
8592993 Method and structure of integrated micro electro-mechanical systems and electronic devices using edge bond pads  
A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region...
8592303 Wiring structure and method for manufacturing the same  
There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a...
8586465 Through silicon via dies and packages  
A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask...
8587124 Semiconductor device having low dielectric insulating film and manufacturing method of the same  
A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films...
8580669 Method for fabricating semiconductor device  
A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first bit line contact over a semiconductor substrate, forming a second bit...
8574964 Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tape  
A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and...
8569160 Device fabrication  
Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device...
8557644 Method for fabricating a monolithic integrated composite group III-V and group IV semiconductor device  
According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor...
8541887 Layered chip package and method of manufacturing same  
A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and...
8502377 Package substrate for bump on trace interconnection  
A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap...
8492260 Processes of forming an electronic device including a feature in a trench  
A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the...
8492198 Microelectronic workpieces with stand-off projections and methods for manufacturing microelectronic devices using such workpieces  
Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member...
8470705 Chip pad resistant to antenna effect and method  
A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in...
8466054 Thermal conduction paths for semiconductor structures  
A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the...
8450154 Oxide based memory with a controlled oxygen vacancy conduction path  
Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first...
8431474 Three dimensional multilayer circuit  
A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template...

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